Patents by Inventor Osamu Onodera

Osamu Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250051769
    Abstract: The present invention provides an antisense oligonucleotide that is formed of 15-22 nucleotides and that is complementary to a nucleic acid including at least 15 consecutive bases in a specific target region of a base sequence of SEQ ID NO: 471, or a pharmaceutically acceptable salt thereof, or hydrates of those.
    Type: Application
    Filed: December 13, 2022
    Publication date: February 13, 2025
    Applicants: NIPPON SHINYAKU CO., LTD., NIIGATA UNIVERSITY
    Inventors: Takao KAWANO, Toshiaki ODE, Akie CHIBA, Osamu ONODERA, Taisuke KATO, Sachiko HIROKAWA
  • Publication number: 20240318181
    Abstract: The present invention provides an antisense oligonucleotide that is formed of 15-22 nucleotides and that is complementary to a nucleic acid including at least 15 consecutive bases in a specific target region of a base sequence of SEQ ID NO: 471, or a pharmaceutically acceptable salt thereof, or hydrates of those.
    Type: Application
    Filed: June 12, 2024
    Publication date: September 26, 2024
    Applicants: NIPPON SHINYAKU CO., LTD., NIIGATA UNIVERSITY
    Inventors: Takao KAWANO, Toshiaki ODE, Akie CHIBA, Osamu ONODERA, Taisuke KATO, Sachiko HIROKAWA
  • Publication number: 20240002856
    Abstract: An antisense nucleic acid targeting intron 6 of TDP-43 mRNA, and including a nucleotide sequence complementary to a sequence consisting of 10 or more consecutive bases in a target sequence, wherein the target sequence is the 96th to 330th or 400th to 530th positions of a nucleotide sequence represented by SEQ ID NO:1.
    Type: Application
    Filed: November 15, 2021
    Publication date: January 4, 2024
    Applicant: NIIGATA UNIVERSITY
    Inventors: Akihiro SUGAI, Osamu ONODERA
  • Patent number: 9567637
    Abstract: The present invention provides a method of diagnosing a cerebrovascular disease in a human comprising the steps of: (a) measuring a mutation of HTRA1 gene in a test sample from said human; and (b) determining if the mutation of HTRA1 gene in said test sample correlates with a cerebrovascular disease in said human.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: February 14, 2017
    Assignee: THE UNIVERSITY OF TOKYO
    Inventors: Shoji Tsuji, Osamu Onodera
  • Publication number: 20120100536
    Abstract: The present invention provides a method of diagnosing a cerebrovascular disease in a human comprising the steps of: (a) measuring a mutation of HTRA1 gene in a test sample from said human; and (b) determining if the mutation of HTRA1 gene in said test sample correlates with a cerebrovascular disease in said human.
    Type: Application
    Filed: April 20, 2010
    Publication date: April 26, 2012
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Shoji Tsuji, Osamu Onodera
  • Patent number: 7726820
    Abstract: A cabinet of a projection type display unit includes a base cabinet on which main component parts are mounted, and a top cover made from sheet metal which is mounted so as to cover the base cabinet, wherein a rear face portion of the top cover is formed in the shape of a curved surface being laid-down U-shaped in side view. The U-shaped curved surface is formed on an ergonomic basis, so that the rear face portion can be gripped securely even with one hand. On the back side of the top cover, bosses are integrally formed by use of a resin which is a different material from the sheet metal of the top cover, and the base cabinet and the top cover are fixed by fastening screws to the bosses from the base cabinet side.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: June 1, 2010
    Assignee: Sony Corporation
    Inventors: Nobuyuki Hara, Shinichi Ueda, Makoto Nagata, Yoshihisa Wada, Dai Yoneya, Osamu Onodera
  • Publication number: 20070070298
    Abstract: An armor cabinet of a projection type display unit includes a base cabinet on which main component parts are mounted, and a top cover made from sheet metal which is mounted so as to cover the base cabinet, wherein a rear face portion composed of the top cover is formed in the shape of a curved surface being laid-down U-shaped in side view. At the time of carrying the projection type display unit, the rear face portion in the U-shaped curved surface shape is just fitted to the palm on an ergonomic basis, and the grip can range to the fingertips, so that the rear face portion can be gripped assuredly and securely even with one hand. On the back side of the top cover, bosses are integrally formed by use of a resin which is a different material from the sheet metal of the top cover, and the base cabinet and the top cover are fixed by fastening screws to the bosses from the base cabinet side.
    Type: Application
    Filed: May 25, 2006
    Publication date: March 29, 2007
    Inventors: Nobuyuki Hara, Shinichi Ueda, Makoto Nagata, Yoshihisa Wada, Dai Yoneya, Osamu Onodera
  • Patent number: 6950278
    Abstract: A magnetic head having a sliding surface (120) on which a magnetic recording medium is slid, a magnetic gap g formed in the sliding surface for exchanging information signals with the magnetic recording medium, a track width controlling portion for prescribing a track width Tw of the magnetic gap g, with the track width controlling portion being formed by abutting a pair of magnetic core halves (110a, 110b) together, there being track width controlling grooves (111a to 111d) formed in each of the magnetic core halves, metal magnetic films (112a to 112f) provided in association with the magnetic gap g and with the track width controlling portion, and a groove (130) formed in at least one end of the magnetic gap g for extending substantially parallel to the sliding direction of the magnetic recording medium.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: September 27, 2005
    Assignee: Sony Corporation
    Inventors: Osamu Onodera, Heikichi Sato, Katsumi Sakata, Kaoru Aoki
  • Publication number: 20050162777
    Abstract: A magnetic head having a sliding surface (120) on which a magnetic recording medium is slid, a magnetic gap g formed in the sliding surface for exchanging information signals with the magnetic recording medium, a track width controlling portion for prescribing a track width Tw of the magnetic gap g, with the track width controlling portion being formed by abutting a pair of magnetic core halves (110a, 110b) together, there being track width controlling grooves (111a to 111d) formed in each of the magnetic core halves, metal magnetic films (112a to 112f) provided in association with the magnetic gap g and with the track width controlling portion, and a groove (130) formed in at least one end of the magnetic gap g for extending substantially parallel to the sliding direction of the magnetic recording medium.
    Type: Application
    Filed: March 23, 2005
    Publication date: July 28, 2005
    Inventors: Osamu Onodera, Heikichi Sato, Katsumi Sakata, Kaoru Aoki
  • Patent number: 6894868
    Abstract: A magnetic head having a sliding surface (120) on which a magnetic recording medium is slid, a magnetic gap g formed in the sliding surface for exchanging information signals with the magnetic recording medium, a track width controlling portion for prescribing a track width Tw of the magnetic gap g, with the track width controlling portion being formed by abutting a pair of magnetic core halves (110a, 110b) together, there being track width controlling grooves (111a to 111d) formed in each of the magnetic core halves, metal magnetic films (112a to 112f) provided in association with the magnetic gap g and with the track width controlling portion, and a groove (130) formed in at least one end of the magnetic gap g for extending substantially parallel to the sliding direction of the magnetic recording medium.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: May 17, 2005
    Assignee: Sony Corporation
    Inventors: Osamu Onodera, Heikichi Sato, Katsumi Sakata, Kaoru Aoki
  • Publication number: 20040100726
    Abstract: A magnetic head having a sliding surface (120) on which a magnetic recording medium is slid, a magnetic gap g formed in the sliding surface for exchanging information signals with the magnetic recording medium, a track width controlling portion for prescribing a track width Tw of the magnetic gap g, with the track width controlling portion being formed by abutting a pair of magnetic core halves (110a, 110b) together, there being track width controlling grooves (111a to 111d) formed in each of the magnetic core halves, metal magnetic films (112a to 112f) provided in association with the magnetic gap g and with the track width controlling portion, and a groove (130) formed in at least one end of the magnetic gap g for extending substantially parallel to the sliding direction of the magnetic recording medium.
    Type: Application
    Filed: August 28, 2003
    Publication date: May 27, 2004
    Inventors: Osamu Onodera, Heikichi Sato, Katsumi Sakata, Kaoru Aoki
  • Patent number: 6324630
    Abstract: A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: November 27, 2001
    Assignee: Hitachi, Ltd.
    Inventor: Osamu Onodera
  • Patent number: 6128714
    Abstract: A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: October 3, 2000
    Assignee: Hitachi, Ltd.
    Inventor: Osamu Onodera
  • Patent number: 5996026
    Abstract: A connection method of a plurality of input/output channels between a plurality of sub-channels of an information processing system having a virtual machine running on a physical machine under control of a hypervisor and a plurality of devices. The method includes issuing from the hypervisor a command for setting configuration information defining a plurality of configuration structures between the sub-channels set for the respective virtual machines and the devices in a storage device and acquiring configuration information containing the sub-channel corresponding to a designated device from the configuration information corresponding to one of the virtual machines based on the device designation contained in the input/output command from the one virtual machine. The virtual machines are enabled after the issuance of the set command and before the issuance of the input/output command.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: November 30, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Onodera, Makiko Shinohara, Kiichi Sato
  • Patent number: 5898855
    Abstract: A virtual machine system capable of considerably improving its performance by preventing a variation of time slice values of logical processors and strictly ensuring the concurrent running of a plurality of logical processors belonging to the same virtual machine, in the configuration and management of virtual machines of a multi-processor structure having a plurality of logical processors. A method of controlling a virtual machine running time in the virtual machine system includes collectively storing time slice values of logical processors in a virtual machine to which the logical processors belong, and making a virtual machine control program for supervising and controlling the logical processors to store and manage the time slice values.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: April 27, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Onodera, Ken Uehara
  • Patent number: 5845146
    Abstract: An extending system in an information processing system which includes an input/output channel and operates a plurality of virtual computers. A plurality of input/output processing units are included in the input/output channel and each virtual computer issues a region ID and a channel path ID. A channel path reconfiguration array is provided having a plurality of channel path reconfiguration array blocks corresponding to region IDs. Each channel path reconfiguration array block includes a plurality of channel path reconfiguration array entries corresponding to channel path IDs and each channel path reconfiguration array entry includes an input/output processing unit number and a channel path ID.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: December 1, 1998
    Assignee: Hitachi, Ltd.
    Inventor: Osamu Onodera
  • Patent number: 5684974
    Abstract: An apparatus and method for controlling the reconfiguration of the physical storage area in a real storage device employed by an information processing system.The invention includes an address reconfiguration array having a plurality of storage blocks which are each assigned to a virtual computer. Each storage block is composed of a plurality of host real-address entries. Assigned to a storage area in the logical memory of a virtual computer, each host real-address entry includes a validity field containing a validity bit and a host real-address field containing a high-order part of the start address of a real storage segment allocated to the storage area. The invention also includes a selector which receives the identifier of a virtual computer and a logical address from the virtual computer, and makes use of the identifier for choosing a storage block from the address reconfiguration array and a high-order portion of the logical address for selecting a host real-address entry from the chosen storage block.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: November 4, 1997
    Assignee: Hitachi, Ltd.
    Inventor: Osamu Onodera
  • Patent number: 5592638
    Abstract: When virtual machines are activated under a condition in which an assignment request having a storage extent and a storage region origin is designated and an assignment request having only the storage extent designated are mixedly present, the logical partion (LPAR) whose storage origin is designated by flags is regarded as already assigned even when the storage region is not actually assigned, and a work table indicative of the current status of the storage assignment is generated in a not-in-use storage region table. The not-in-use storage region table is generated on the basis of the work table to determine the assignment or non-assignment of the LPAR to be activated, and assignment or non-assignment of a plurality of such not-in-use regions can be judged in an ascending order.
    Type: Grant
    Filed: July 13, 1993
    Date of Patent: January 7, 1997
    Assignee: Hitachi, Ltd.
    Inventor: Osamu Onodera
  • Patent number: 5574878
    Abstract: A method fr purging a translation lookaside buffer purges only those entries required to be purged in order to eliminate overhead incurring degradation in the use efficiency of the translation lookaside buffer. The buffer is employed in a virtual machine system containing a plurality of levels of virtual machines and at least one register for storing virtual machine identification codes. Upon execution of an instruction, which is issued by a particular one of the virtual machines and which is accompanied by a purge of the translation lookaside buffer, the virtual machine identification code of the particular virtual machine and a virtual machine identification code of another virtual machine having a translation lookaside buffer entry to be purged are stored in the register.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: November 12, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Onodera, Ken Uehara, Yuji Kobayashi, Hideaki Amano
  • Patent number: 5530820
    Abstract: A level-2 virtual machine is constructed under the control of a level-1 operating system (OS) operating on a real machine (level-1), and a level-3 virtual machine is constructed under the control of another operating system (OS) operating on the level-2 virtual machine. A level-3 virtual address generated in the level-3 virtual machine is translated to a level-2 virtual address, which is further translated to a level-1 virtual address. A third predetermined main storage address is added to the level-1 virtual address to generate a level-1 absolute address. The translated address is checked as to whether it is within a predetermined area on the main storage.
    Type: Grant
    Filed: October 25, 1994
    Date of Patent: June 25, 1996
    Assignee: Hitachi, Ltd.
    Inventor: Osamu Onodera