Patents by Inventor Osamu OOTO

Osamu OOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device, method for designing semiconductor memory device, and recording medium having designing method recorded therein
    Patent number: 9639649
    Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: May 2, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi Etou, Jumpei Sato, Satoshi Yamano, Osamu Ooto, Souichi Minemura
  • SEMICONDUCTOR MEMORY DEVICE, METHOD FOR DESIGNING SEMICONDUCTOR MEMORY DEVICE, AND RECORDING MEDIUM HAVING DESIGNING METHOD RECORDED THEREIN
    Publication number: 20170053053
    Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.
    Type: Application
    Filed: November 11, 2015
    Publication date: February 23, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi ETOU, Jumpei SATO, Satoshi YAMANO, Osamu OOTO, Souichi MINEMURA