Abstract: Disclosed is a wafer-scale chip structure including a semiconductor wafer and multiple dies on the semiconductor wafer. The dies can include at least two dies with different patterns of fill shapes. Also disclosed are wafer-scale chip design methods and systems. In the design methods and systems, post-chip layout wafer-level topography optimization is performed to, for example, minimize performance variations between dies of the same design within the wafer-scale chip. Specifically, across-wafer die placement and wafer-level topography information is used to custom design and/or select different patterns of fill shapes to be inserted into the layouts of dies placed at different locations across the wafer-scale chip (including different patterns to be inserted into the layouts of dies that have the same design) in order to generate a design that minimizes either all across-wafer thickness variations or at least across-wafer thickness variations associated with specific dies having the same specific design.

Abstract: Embodiments of the present invention include systems and methods of controlling reticle transmission. A process window for reticle transmission is received. For a given design, default fill cells of a default fill pattern are inserted in unused areas of an integrated circuit (IC). A pattern density is computed for each tile of an IC at each appropriate level, such as metallization levels and contact levels. An IC reticle transmission (RT) is computed for an area corresponding to an entire (or area of) IC or reticle. If the integrated circuit RT is outside of the process window, then the tiles that have an individual tile RT that is outside of the process window are identified and ranked into groups. Default fill cells in one group of tiles are replaced with replacement fill cells having an appropriate pattern and pattern density, and an updated IC RT parameter is computed until the updated IC RT parameter is within the process window.

Abstract: Embodiments of the present invention include systems and methods of controlling reticle transmission. A process window for reticle transmission is received. For a given design, default fill cells of a default fill pattern are inserted in unused areas of an integrated circuit (IC). A pattern density is computed for each tile of an IC at each appropriate level, such as metallization levels and contact levels. An IC reticle transmission (RT) is computed for an area corresponding to an entire (or area of) IC or reticle. If the integrated circuit RT is outside of the process window, then the tiles that have an individual tile RT that is outside of the process window are identified and ranked into groups. Default fill cells in one group of tiles are replaced with replacement fill cells having an appropriate pattern and pattern density, and an updated IC RT parameter is computed until the updated IC RT parameter is within the process window.

Abstract: A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.

Abstract: A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.