Abstract: In an output mode, an output switch (SW11) is turned on and supply switches (SW13a, SW13b) are turned off, and output current is supplied to an intermediate node (nc) from driving transistors (T105a, T105b). In a transition mode, the output switch (SW11) is turned off and the supply switches (SW13a, SW13b) are turned on, and supply of the output current from the driving transistors (T105a, T105b) is shut off. Meanwhile, capacitance elements (C103a, C103b) receive voltage from reference nodes (Vcc, Vss). Also input voltage (Vin) is supplied to the intermediate node (nc).

Abstract: In an output mode, an output switch (SW11) is turned on and supply switches (SW13a, SW13b) are turned off, and output current is supplied to an intermediate node (nc) from driving transistors (T105a, T105b). In a transition mode, the output switch (SW11) is turned off and the supply switches (SW13a, SW13b) are turned on, and supply of the output current from the driving transistors (T105a, T105b) is shut off. Meanwhile, capacitance elements (C103a, C103b) receive voltage from reference nodes (Vcc, Vss). Also input voltage (Vin) is supplied to the intermediate node (nc).

Abstract: In an output mode, an output switch (SW11) is turned on and supply switches (SW13a, SW13b) are turned off, and output current is supplied to an intermediate node (nc) from driving transistors (T105a, T105b). In a transition mode, the output switch (SW11) is turned off and the supply switches (SW13a, SW13b) are turned on, and supply of the output current from the driving transistors (T105a, T105b) is shut off. Meanwhile, capacitance elements (C103a, C103b) receive voltage from reference nodes (Vcc, Vss). Also input voltage (Vin) is supplied to the intermediate node (nc).

Abstract: In a LCD device, deterioration in display quality due to the difference of the line resistances of scan-line control signal lines is prevented by a simple structure. A gate driver outputs, from respective output terminals connected to scan-line control signal lines of a liquid crystal panel, a panel control pulse for turning on a TFT. A timing control circuit outputs to the gate driver an output enable signal for controlling an output timing of the panel control pulse. The output enable signal includes an enable control pulse for enabling the panel control pulse to be output. The timing control circuit is capable of adjusting the pulse width of the enable control pulse in accordance with the output terminals of the gate driver.

Abstract: A driving device for driving an image display system, which sequentially receives input image data corresponding to gradation of each pixel of a display image and outputs a driving voltage signal includes: an operation section for obtaining output image data of which a bit number is smaller than a bit number of the input image data based on input image data of a target pixel to be processed and input image data of a pixel in vicinity of the target pixel; a reference voltage generation section for generating a plurality of reference voltages of different levels; and a reference voltage selection section for selecting one of the plurality of reference voltages. The operation section is configured to obtain output image data of the target pixel so that a difference between the input image data and output image data of the target pixel and a difference between the input image data and output image data of the pixel in vicinity of the target pixel cancel out each other.

Abstract: In an output mode, an output switch (SW11) is turned on and supply switches (SW13a, SW13b) are turned off, and output current is supplied to an intermediate node (nc) from driving transistors (T105a, T105b). In a transition mode, the output switch (SW11) is turned off and the supply switches (SW13a, SW13b) are turned on, and supply of the output current from the driving transistors (T105a, T105b) is shut off. Meanwhile, capacitance elements (C103a, C103b) receive voltage from reference nodes (Vcc, Vss). Also input voltage (Vin) is supplied to the intermediate node (nc).

Abstract: If a display is subjected to n line dot inversion drive control, the polarity pattern of sub-pixels is shifted line by line in a cycle of n frames. Furthermore, in every n horizontal scanning periods in which the polarities of output terminals of a source driver are switched, at least two of the output terminals are short-circuited to carry out electrical charge recovery. By using these methods, it is possible to achieve a reduction in power consumption while improving image quality.

Abstract: A level shift circuit having a latch function includes a precharging PMOS transistor MP1 which is turned on in a precharge period to interrupt a through current of an input stage, an NMOS transistor MN1 which inputs data and performs discharging in a data input period, and a transistor MP2 for holding data after level shifting. Thus, each of the transistors can have a minimum configuration. Since the level shift circuit has a latch function, it is possible to omit a circuit for latching input data, thereby reducing a circuit area.

Abstract: A signal line driving circuit includes an output section outN (where N is a natural number) for supplying an image-forming signal for red, green or blue to a sub-pixel of a display section, a voltage supply line SN connected to the output section outN, and a shorting line for electrically shorting output sections of the same color with each other during a predetermined period. By shorting output sections of the same color with each other, the charge stored in a panel-side load can be effectively redistributed to another panel-side load, thereby realizing a power conserving effect.

Abstract: A level shift circuit having a latch function includes a precharging PMOS transistor MP1 which is turned on in a precharge period to interrupt a through current of an input stage, an NMOS transistor MN1 which inputs data and performs discharging in a data input period, and a transistor MP2 for holding data after level shifting. Thus, each of the transistors can have a minimum configuration. Since the level shift circuit has a latch function, it is possible to omit a circuit for latching input data, thereby reducing a circuit area.

Abstract: If a display is subjected to n line dot inversion drive control, the polarity pattern of sub-pixels is shifted line by line in a cycle of n frames. Furthermore, in every n horizontal scanning periods in which the polarities of output terminals of a source driver are switched, at least two of the output terminals are short-circuited to carry out electrical charge recovery. By using these methods, it is possible to achieve a reduction in power consumption while improving image quality.

Abstract: A signal line driving circuit includes an output section outN (where N is a natural number) for supplying an image-forming signal for red, green or blue to a sub-pixel of a display section, a voltage supply line SN connected to the output section outN, and a shorting line for electrically shorting output sections of the same color with each other during a predetermined period. By shorting output sections of the same color with each other, the charge stored in a panel-side load can be effectively redistributed to another panel-side load, thereby realizing a power conserving effect.

Abstract: A differential amplifier achieving a high throughput rate with reduced power consumption includes a differential circuit, output circuit, a constant current source transistor, a drive transistor, and a switching circuit. A difference voltage relative to a difference between voltages applied to non-inverting and inverting inputs of the differential circuit is applied to the switching circuit. The switching circuit supplies a drive signal to the drive transistor to enable the drive transistor when the difference voltage is below a predetermined threshold voltage, and to disable the drive transistor when the difference voltage is above the predetermined threshold voltage.