Abstract: An asynchronous signal synchronizing circuit for sampling and external asynchronous signal in a quarter of the period of a clock. A first latch circuit latches asynchronous input signal in accordance with a first clock, and a second latch circuit latches the output of the first latch circuit in accordance with a second clock having a phase shift 180.degree. out of phase with the first clock. A third latch circuit latches the output signal of the second latch signal in accordance with a clock signal that represents the inverse of the first clock. A fourth latch circuit latches the output signal of the third latch circuit under the control of a clock that corresponds to the inverse of the second clock. The asynchronous input signal is sampled at the tailing edge of the first clock signal and validated by the tailing edge of the second clock signal. The synchronization of the asynchronous signal can thus be performed in a quarter of a clock cycle.