Patents by Inventor Osamu Soma

Osamu Soma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125665
    Abstract: In a charging device, a terminal device including a power receiver coil that receives wirelessly transmitted power is placed on a charging stand to perform noncontact charging. The charging device includes a power transmitter coil, a memory, and a processor coupled to the memory. The power transmitter coil transmits electric power to the terminal device. The processor is configured to: cause the power transmitter coil to transmit electric power; acquire magnitude of transmitted power that the processor causes to be transmitted; acquire magnitude of received power received by the power receiver coil; calculate a ratio of the received power to the transmitted power; and limit the transmitted power in a case where the ratio is smaller than a threshold.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Applicant: Panasonic Automotive Systems Co., Ltd.
    Inventor: Osamu SOMA
  • Patent number: 11128131
    Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naohiro Yoshimura, Osamu Soma
  • Patent number: 10859624
    Abstract: A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: December 8, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira Uemura, Osamu Soma
  • Patent number: 10840898
    Abstract: A semiconductor device and electronic control device capable of shutting off the reverse current flow from a load to a power supply is provided. The power transistor QN1 is provided between the positive power supply terminal Pi2(+) and the load-driving terminal Po2(+), and has a source and a back-gate coupled to the positive power supply terminal Pi2(+). The power transistor QN2 is provided in series with the power transistor QN1, and its sources and backgates are coupled to the load-driving terminal Po2(+). The booster CP1a charges the gates of the power transistors QN1. The gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source when the potential of the negative power supply terminal Pi2(?) is higher than the potential of the positive power supply terminal Pi2(+).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 17, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Osamu Soma
  • Publication number: 20200091714
    Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 19, 2020
    Inventors: Naohiro YOSHIMURA, Osamu SOMA
  • Publication number: 20200028503
    Abstract: A semiconductor device and electronic control device capable of shutting off the reverse current flow from a load to a power supply is provided. The power transistor QN1 is provided between the positive power supply terminal Pi2(+) and the load-driving terminal Po2(+), and has a source and a back-gate coupled to the positive power supply terminal Pi2(+). The power transistor QN2 is provided in series with the power transistor QN1, and its sources and backgates are coupled to the load-driving terminal Po2(+). The booster CP1a charges the gates of the power transistors QN1. The gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source when the potential of the negative power supply terminal Pi2(?) is higher than the potential of the positive power supply terminal Pi2(+).
    Type: Application
    Filed: June 25, 2019
    Publication date: January 23, 2020
    Inventor: Osamu SOMA
  • Patent number: 10222403
    Abstract: A control method of a semiconductor device includes inspecting an electrical property of a current detection circuit in the first semiconductor chip, writing information on a correction equation obtained on the basis of an inspection result in a memory circuit of the second semiconductor chip, and correcting, with the second semiconductor chip, a detection result obtained by the current detection circuit on the basis of the information on the correction equation.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Soma, Akira Uemura, Kenji Amada
  • Patent number: 10115251
    Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 30, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Soma, Akira Uemura
  • Publication number: 20180080963
    Abstract: A control method of a semiconductor device includes inspecting an electrical property of a current detection circuit in the first semiconductor chip, writing information on a correction equation obtained on the basis of an inspection result in a memory circuit of the second semiconductor chip, and correcting, with the second semiconductor chip, a detection result obtained by the current detection circuit on the basis of the information on the correction equation.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Inventors: Osamu SOMA, Akira Uemura, Kenji Amada
  • Patent number: 9835660
    Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: December 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Soma, Akira Uemura, Kenji Amada
  • Publication number: 20170184658
    Abstract: A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 29, 2017
    Inventors: Akira Uemura, Osamu Soma
  • Patent number: 9530721
    Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nishikizawa, Tadatoshi Danno, Hiroyuki Nakamura, Osamu Soma, Akira Uemura
  • Publication number: 20160365721
    Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.
    Type: Application
    Filed: April 28, 2016
    Publication date: December 15, 2016
    Inventors: Osamu SOMA, Akira UEMURA
  • Patent number: 9500704
    Abstract: A semiconductor device includes: a drive circuit; a standby circuit; and a detection circuit. The drive circuit turns on an output transistor connected to a load based on an active input signal. The standby circuit intermittently outputs an output signal based on a non-active input signal. The detection circuit measures voltage of a load side of the output transistor based on the output signal and output a measurement result.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Osamu Soma
  • Publication number: 20160305989
    Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.
    Type: Application
    Filed: March 14, 2016
    Publication date: October 20, 2016
    Inventors: Osamu SOMA, Akira Uemura, Kenji Amada
  • Publication number: 20160093557
    Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 31, 2016
    Inventors: Atsushi NISHIKIZAWA, Tadatoshi DANNO, Hiroyuki NAKAMURA, Osamu SOMA, Akira UEMURA
  • Publication number: 20140239988
    Abstract: A semiconductor device includes: a drive circuit; a standby circuit; and a detection circuit. The drive circuit turns on an output transistor connected to a load based on an active input signal. The standby circuit intermittently outputs an output signal based on a non-active input signal. The detection circuit measures voltage of a load side of the output transistor based on the output signal and output a measurement result.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 28, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Osamu SOMA
  • Patent number: 8373494
    Abstract: A power supply control circuit comprises an output transistor which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor 32 based on an external input signal. A transistor 37 discharges a gate charge of the output transistor based on the control signals “a” and “b”, when turning off the output transistor. A transistor 39 discharges more slowly than the transistor. A diode is coupled to the transistor 37 in series and which cuts off a discharge path through the transistor 37 transistor and the diode when the gate voltage of the output transistor falls to a voltage level higher than the sum of the power supply voltage Vcc and a threshold voltage of the output transistor, at a time of turning off the output transistor.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Soma, Akihiro Nakahara
  • Patent number: 8242830
    Abstract: A power supply control circuit comprises an output transistor 32 which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor based on an external input signal. A first discharge path includes a first depletion-type N-channel MOS transistor provided between a gate and a source of the output transistor and discharges a gate charge of the output transistor based on the control signals, when turning off the output transistor. A second discharge path includes a first depletion-type N-channel MOS transistor discharges more slowly than the first discharge path. A diode is coupled to the first depletion-type N-channel MOS transistor in series and detects that a gate voltage of the output transistor has fallen to a prescribed voltage level, and cuts off a first discharge path.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Soma, Akihiro Nakahara
  • Publication number: 20110163794
    Abstract: A power supply control circuit comprises an output transistor which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor 32 based on an external input signal. A transistor 37 discharges a gate charge of the output transistor based on the control signals “a” and “b”, when turning off the output transistor. A transistor 39 discharges more slowly than the transistor. A diode is coupled to the transistor 37 in series and which cuts off a discharge path through the transistor 37 transistor and the diode when the gate voltage of the output transistor falls to a voltage level higher than the sum of the power supply voltage Vcc and a threshold voltage of the output transistor, at a time of turning off the output transistor.
    Type: Application
    Filed: December 27, 2010
    Publication date: July 7, 2011
    Inventors: Osamu SOMA, Akihiro Nakahara