Abstract: An optical and electronic integrated switch includes a network processor that controls the functions of the packet switch, a plurality of optical transceivers having photoelectric conversion functions, and a plurality of optical switches. The optical switches include different types of optical core switch and a plurality of optical-path selection switches. The optical transceivers provided near the processor have a regenerative relay function that regenerates optical signals and turns back the optical signals, and perform optical communication with a communication counterpart via the optical switches. In the optical communication, optical switches of the different types can cooperate to set paths for optical cut-through in which path selection is performed such that inputted optical signals are outputted without the intervention of the processor. This optical cut-through can be effectively performed without imposing a signal processing burden that consumes electric power on the processor.

Abstract: A photonics-electronics convergence switch with which, even if an optical network system is built by combining a plurality of packet switches, the amount of processing in the packet switches does not increase, the optical network system operates with low electric power consumption, and this enables wide-range optical communication between the nodes of a communication origin and of a communication partner, includes a network processor that is an electronic circuit configured to control the functions of the packet switch, a plurality of optical transmitter-receivers having photoelectric conversion functions, and a plurality of optical switches.

Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.

Abstract: A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

Abstract: A semiconductor device and electronic control device capable of shutting off the reverse current flow from a load to a power supply is provided. The power transistor QN1 is provided between the positive power supply terminal Pi2(+) and the load-driving terminal Po2(+), and has a source and a back-gate coupled to the positive power supply terminal Pi2(+). The power transistor QN2 is provided in series with the power transistor QN1, and its sources and backgates are coupled to the load-driving terminal Po2(+). The booster CP1a charges the gates of the power transistors QN1. The gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source when the potential of the negative power supply terminal Pi2(?) is higher than the potential of the positive power supply terminal Pi2(+).

Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.

Abstract: A semiconductor device and electronic control device capable of shutting off the reverse current flow from a load to a power supply is provided. The power transistor QN1 is provided between the positive power supply terminal Pi2(+) and the load-driving terminal Po2(+), and has a source and a back-gate coupled to the positive power supply terminal Pi2(+). The power transistor QN2 is provided in series with the power transistor QN1, and its sources and backgates are coupled to the load-driving terminal Po2(+). The booster CP1a charges the gates of the power transistors QN1. The gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source when the potential of the negative power supply terminal Pi2(?) is higher than the potential of the positive power supply terminal Pi2(+).

Abstract: A control method of a semiconductor device includes inspecting an electrical property of a current detection circuit in the first semiconductor chip, writing information on a correction equation obtained on the basis of an inspection result in a memory circuit of the second semiconductor chip, and correcting, with the second semiconductor chip, a detection result obtained by the current detection circuit on the basis of the information on the correction equation.

Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.

Abstract: A control method of a semiconductor device includes inspecting an electrical property of a current detection circuit in the first semiconductor chip, writing information on a correction equation obtained on the basis of an inspection result in a memory circuit of the second semiconductor chip, and correcting, with the second semiconductor chip, a detection result obtained by the current detection circuit on the basis of the information on the correction equation.

Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.

Abstract: A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.

Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.

Abstract: A semiconductor device includes: a drive circuit; a standby circuit; and a detection circuit. The drive circuit turns on an output transistor connected to a load based on an active input signal. The standby circuit intermittently outputs an output signal based on a non-active input signal. The detection circuit measures voltage of a load side of the output transistor based on the output signal and output a measurement result.

Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.

Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.

Abstract: A semiconductor device includes: a drive circuit; a standby circuit; and a detection circuit. The drive circuit turns on an output transistor connected to a load based on an active input signal. The standby circuit intermittently outputs an output signal based on a non-active input signal. The detection circuit measures voltage of a load side of the output transistor based on the output signal and output a measurement result.

Abstract: A power supply control circuit comprises an output transistor which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor 32 based on an external input signal. A transistor 37 discharges a gate charge of the output transistor based on the control signals “a” and “b”, when turning off the output transistor. A transistor 39 discharges more slowly than the transistor. A diode is coupled to the transistor 37 in series and which cuts off a discharge path through the transistor 37 transistor and the diode when the gate voltage of the output transistor falls to a voltage level higher than the sum of the power supply voltage Vcc and a threshold voltage of the output transistor, at a time of turning off the output transistor.

Abstract: A power supply control circuit comprises an output transistor 32 which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor based on an external input signal. A first discharge path includes a first depletion-type N-channel MOS transistor provided between a gate and a source of the output transistor and discharges a gate charge of the output transistor based on the control signals, when turning off the output transistor. A second discharge path includes a first depletion-type N-channel MOS transistor discharges more slowly than the first discharge path. A diode is coupled to the first depletion-type N-channel MOS transistor in series and detects that a gate voltage of the output transistor has fallen to a prescribed voltage level, and cuts off a first discharge path.