Abstract: A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or more after all the subject wafers are loaded in the container while the side door is open.

Abstract: A touch panel capable of decreasing concavity and convexity generated on the surface and a display unit including the same are provided. The touch panel includes: a first spacer layer on both side faces of a first wiring layer provided on a first transparent substrate; and a second wiring layer on both side faces of a second wiring layer provided on a second transparent substrate. The touch panel also includes a flexible printed circuit board in a gap between the first transparent substrate and the second transparent substrate and in a region including at least part of a region not provided with the adhesion layer in the region opposed to the first wiring layer, the second wiring layer, the first spacer layer, and the second spacer layer.

Abstract: A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or more after all the subject wafers are loaded in the container while the side door is open.

Abstract: A touch panel capable of decreasing concavity and convexity generated on the surface and a display unit including the same are provided. The touch panel includes: a first spacer layer on both side faces of a first wiring layer provided on a first transparent substrate; and a second wiring layer on both side faces of a second wiring layer provided on a second transparent substrate. The touch panel also includes a flexible printed circuit board in a gap between the first transparent substrate and the second transparent substrate and in a region including at least part of a region not provided with the adhesion layer in the region opposed to the first wiring layer, the second wiring layer, the first spacer layer, and the second spacer layer.

Abstract: A scan-chain extracting method of the present invention includes a defining step of defining control-circuit scan chains provided in a test control circuit; an initial-value setting step of setting an initial value for the sequence circuit devices of the control-circuit scan chains; a state setting step of setting the scan chains to through states; an extracting step of extracting data regarding the scan chains; a determining step of determining whether or not data regarding all the scan chains have been extracted; and a changing step of changing the initial value for the sequence circuit devices included in the test control circuit connected to the sequence circuit devices located at the start points of the scan chains, when it is determined that not all data regarding the scan chains have been extracted.

Abstract: A scan-chain extracting method of the present invention includes a defining step of defining control-circuit scan chains provided in a test control circuit; an initial-value setting step of setting an initial value for the sequence circuit devices of the control-circuit scan chains; a state setting step of setting the scan chains to through states; an extracting step of extracting data regarding the scan chains; a determining step of determining whether or not data regarding all the scan chains have been extracted; and a changing step of changing the initial value for the sequence circuit devices included in the test control circuit connected to the sequence circuit devices located at the start points of the scan chains, when it is determined that not all data regarding the scan chains have been extracted.

Abstract: A method for forming a semiconductor device having an isolation trench for separation of element regions includes the steps of forming a pad oxide film and a silicon nitride film on a silicon substrate, forming an isolation trench by using the silicon nitride film as a mask, forming consecutively a thermal oxide film, CVD oxide film and a bias oxide film in the isolation trench, removing the films above a specified level of the silicon substrate to leave the isolation trench filled with oxide films. The bias oxide film is formed by a high-density plasma CVD technique. The silicon surface is protected by the CVD oxide film against the plasma damage during the high-density CVD step, thereby obtaining excellent characteristics of transistors.