Patents by Inventor Osamu Tachibana

Osamu Tachibana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5481489
    Abstract: When processing a binary floating-point number in the IEEE form, whether or not the data is NaN can be discriminated irrespective of a precision thereof. The binary floating-point number having sign, exponent and fraction parts is based on the IEEE form in which the data is defined as NaN on condition that "all values of respective bits of the exponent part are `1`, and all values of respective bits of the fraction part are not `0`". In this binary floating-point number, if a precision of the binary floating-point is the maximum precision, the data is set intactly as internal representation form data. If the precision is less than the maximum precision, the following transform is executed. The sign part is set as it is. The exponent part is extended to a number of bits of the exponent part of the maximum precision, and deficient bits due to this extension are filled with `1`.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: January 2, 1996
    Assignee: Fujitsu Limited
    Inventors: Masahiro Yanagida, Hiromasa Takahashi, Osamu Tachibana