Patents by Inventor Osamu Takata

Osamu Takata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230122223
    Abstract: An article inspection apparatus inspects a workpiece W including a plurality of ingredients Wa, Wb, Wc, and Wd by using an inspection image of the workpiece. The article inspection apparatus includes an X-ray image memory 61 that stores information of a predetermined detection value related to the inspection image, a configuration determination unit 53 that determines a material configuration of a content in the workpiece W by performing predetermined recognition processing based on image data of the workpiece W obtained by capturing of the camera 41, and a proposal output unit 54 that, when the configuration determination unit 53 determines the material configuration of the content, estimates detection sensitivity to the predetermined detection value based on information stored in the X-ray image memory 61 and a management sensitivity memory 64, and proposes and outputs a determination criterion for an article inspection.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 20, 2023
    Inventors: Osamu TAKATA, Shinya WAKI
  • Patent number: 11355495
    Abstract: A semiconductor device includes first to sixth transistors of enhancement type. The first and fourth transistors are of p-channel type. The second, third, fifth and sixth transistors are of n-channel type. A breakdown voltage of the third transistor is lower than a breakdown voltage of the second transistor. A breakdown voltage of the sixth transistor is lower than a breakdown voltage of the fifth transistor. The first to third transistors are connected in series between a first power supply potential and a second power supply potential lower than the first power supply potential. The fourth to sixth transistors are connected in series between the first power supply potential and the second power supply potential.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 7, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hidekazu Inoto, Osamu Takata, Naozumi Terada, Hiroyoshi Kitahara
  • Patent number: 11132782
    Abstract: Included are an inspection unit that outputs a detection signal corresponding to type and size of a foreign matter contained in an inspection object or a detection signal corresponding to weight of the inspection object, a determination unit that performs a pass/fail determination as to the inspection object, based on the detection signal from the inspection unit, an inspection record information accumulation unit that accumulates inspection record information including inspection date and time and inspection data, and a control unit that displays on a display operation unit, a list of inspection data of an inspection object having a defective inspection result from the inspection record information, and if one inspection object is selected from the inspection objects displayed as the list by an operation on the display operation unit, displays on the display operation unit, the inspection data in a predetermined range with reference to the selected inspection object.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 28, 2021
    Assignee: ANRITSU CORPORATION
    Inventor: Osamu Takata
  • Patent number: 11121264
    Abstract: A junction field effect transistor includes a first semiconductor layer of first conductivity type, an element isolation insulator disposed on the first semiconductor layer to partition an active area, a second semiconductor layer of second conductivity type, on the first semiconductor layer in the active area, and having an end in a first direction separated from the element isolation insulator, a source layer of second conductivity type, on the second semiconductor layer, the source layer having an impurity concentration higher than that of the second semiconductor layer, a drain layer of second conductivity type, on the second semiconductor layer, and separated from the source layer in a second direction, the drain layer having an impurity concentration higher than that of the second semiconductor layer, and a gate layer of first conductivity type, on the second semiconductor layer, and between and separated from the source and drain layers.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 14, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hidekazu Inoto, Osamu Takata, Naozumi Terada, Hiroyoshi Kitahara
  • Publication number: 20210066295
    Abstract: A semiconductor device includes first to sixth transistors of enhancement type. The first and fourth transistors are of p-channel type. The second, third, fifth and sixth transistors are of n-channel type. A breakdown voltage of the third transistor is lower than a breakdown voltage of the second transistor. A breakdown voltage of the sixth transistor is lower than a breakdown voltage of the fifth transistor. The first to third transistors are connected in series between a first power supply potential and a second power supply potential lower than the first power supply potential. The fourth to sixth transistors are connected in series between the first power supply potential and the second power supply potential.
    Type: Application
    Filed: January 21, 2020
    Publication date: March 4, 2021
    Inventors: Hidekazu Inoto, Osamu Takata, Naozumi Terada, Hiroyoshi Kitahara
  • Patent number: 10818656
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 27, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hidekazu Inoto, Osamu Takata, Itaru Tamura, Naozumi Terada, Hiroyoshi Kitahara
  • Publication number: 20200287057
    Abstract: A junction field effect transistor includes a first semiconductor layer of first conductivity type, an element isolation insulator disposed on the first semiconductor layer to partition an active area, a second semiconductor layer of second conductivity type, on the first semiconductor layer in the active area, and having an end in a first direction separated from the element isolation insulator, a source layer of second conductivity type, on the second semiconductor layer, the source layer having an impurity concentration higher than that of the second semiconductor layer, a drain layer of second conductivity type, on the second semiconductor layer, and separated from the source layer in a second direction, the drain layer having an impurity concentration higher than that of the second semiconductor layer, and a gate layer of first conductivity type, on the second semiconductor layer, and between and separated from the source and drain layers.
    Type: Application
    Filed: August 22, 2019
    Publication date: September 10, 2020
    Inventors: Hidekazu INOTO, Osamu TAKATA, Naozumi TERADA, Hiroyoshi KITAHARA
  • Publication number: 20200184619
    Abstract: To increase reliability of a determination in operation modes different from in normal inspection of an article inspection apparatus by displaying information that can be checked by a manager with respect to a determination of the article inspection apparatus operated in the operation modes different from in the normal inspection and storing a checking result of the manager. There is provided a host computer 71 that acquires and manages inspection information from an X-ray inspection apparatus 30, a metal detection apparatus 40, and a weight inspection apparatus 50 inspecting an article to be produced via a computer network 70, in which the host computer 71 displays a screen from which a determination is checkable by a manager on a display unit 73 and stores checking information input by the manager in correlation with the inspection information when the inspection information is output through the determination during an operation checking mode.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 11, 2020
    Inventor: Osamu TAKATA
  • Publication number: 20200083218
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.
    Type: Application
    Filed: March 12, 2019
    Publication date: March 12, 2020
    Inventors: Hidekazu Inoto, Osamu Takata, Itaru Tamura, Naozumi Terada, Hiroyoshi Kitahara
  • Publication number: 20190376912
    Abstract: Included are an inspection unit that outputs a detection signal corresponding to type and size of a foreign matter contained in an inspection object or a detection signal corresponding to weight of the inspection object, a determination unit that performs a pass/fail determination as to the inspection object, based on the detection signal from the inspection unit, an inspection record information accumulation unit that accumulates inspection record information including inspection date and time and inspection data, and a control unit that displays on a display operation unit, a list of inspection data of an inspection object having a defective inspection result from the inspection record information, and if one inspection object is selected from the inspection objects displayed as the list by an operation on the display operation unit, displays on the display operation unit, the inspection data in a predetermined range with reference to the selected inspection object.
    Type: Application
    Filed: April 29, 2019
    Publication date: December 12, 2019
    Inventor: Osamu TAKATA
  • Patent number: 10224278
    Abstract: A semiconductor device includes a semiconductor substrate comprising an upper layer portion, a first insulating member located in the upper layer portion of the semiconductor substrate and having one or more corner portions, an electrode located on the semiconductor substrate, wherein the electrode overlies at least one of the corner portions of the first insulating member, and an insulating film located between the semiconductor substrate and the electrode.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Yamamoto, Osamu Takata, Mariko Habu, Shinji Kawahara
  • Publication number: 20180061755
    Abstract: A semiconductor device includes a semiconductor substrate comprising an upper layer portion, a first insulating member located in the upper layer portion of the semiconductor substrate and having one or more corner portions, an electrode located on the semiconductor substrate, wherein the electrode overlies at least one of the corner portions of the first insulating member, and an insulating film located between the semiconductor substrate and the electrode.
    Type: Application
    Filed: February 28, 2017
    Publication date: March 1, 2018
    Inventors: Takeshi YAMAMOTO, Osamu TAKATA, Mariko HABU, Shinji KAWAHARA
  • Patent number: 9379272
    Abstract: A light receiving element includes: a semiconductor layer; an insulating layer; an interconnect layer; and a film. The semiconductor layer includes a light receiving unit configured to convert a signal light incident on the light receiving unit into an electrical signal. The insulating layer is provided on the semiconductor layer. The interconnect layer is provided on the insulating layer. The film is provided on the insulating layer to cover the light receiving unit and be connected to the interconnect layer, the film being made of a metal or a metal nitride.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: June 28, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miki Hidaka, Osamu Takata, Masahito Nishigoori, Yukiko Takiba, Hiroshi Suzunaga, Hiroshi Shimomura
  • Publication number: 20150380594
    Abstract: A light receiving element includes: a semiconductor layer; an insulating layer; an interconnect layer; and a film. The semiconductor layer includes a light receiving unit configured to convert a signal light incident on the light receiving unit into an electrical signal. The insulating layer is provided on the semiconductor layer. The interconnect layer is provided on the insulating layer. The film is provided on the insulating layer to cover the light receiving unit and be connected to the interconnect layer, the film being made of a metal or a metal nitride.
    Type: Application
    Filed: September 11, 2015
    Publication date: December 31, 2015
    Inventors: Miki Hidaka, Osamu Takata, Masahito Nishigoori, Yukiko Takiba, Hiroshi Suzunaga, Hiroshi Shimomura
  • Patent number: 9035381
    Abstract: An aspect of the present embodiment, there is provided a semiconductor device includes a high-voltage element, the high-voltage element including a substrate, a first semiconductor region with a first conductive type on the substrate, an insulating isolation film on the substrate, a second semiconductor region with a second conductive type, the second semiconductor region being provided between the first semiconductor region and the insulating isolation film, a drain region with the second conductive type provided on a surface of the second semiconductor region, an impurity concentration of the drain region being higher than an impurity concentration of the second semiconductor region, a source region with the second conductive type provided on a surface of the first semiconductor, the source region being separated from the drain region, a floating drain region with the second conductive type provided on the surface of the first semiconductor region between the second semiconductor region and the source regio
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 19, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Takata
  • Publication number: 20150076526
    Abstract: A light receiving element includes: a semiconductor layer; an insulating layer; an interconnect layer; and a film. The semiconductor layer includes a light receiving unit configured to convert a signal light incident on the light receiving unit into an electrical signal. The insulating layer is provided on the semiconductor layer. The interconnect layer is provided on the insulating layer. The film is provided on the insulating layer to cover the light receiving unit and be connected to the interconnect layer, the film being made of a metal or a metal nitride.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Miki Hidaka, Osamu Takata, Masahito Nishigoori, Yukiko Takiba, Hiroshi Suzunaga, Hiroshi Shimomura
  • Publication number: 20150069506
    Abstract: An aspect of the present embodiment, there is provided a semiconductor device includes a high-voltage element, the high-voltage element including a substrate, a first semiconductor region with a first conductive type on the substrate, an insulating isolation film on the substrate, a second semiconductor region with a second conductive type, the second semiconductor region being provided between the first semiconductor region and the insulating isolation film, a drain region with the second conductive type provided on a surface of the second semiconductor region, an impurity concentration of the drain region being higher than an impurity concentration of the second semiconductor region, a source region with the second conductive type provided on a surface of the first semiconductor, the source region being separated from the drain region, a floating drain region with the second conductive type provided on the surface of the first semiconductor region between the second semiconductor region and the source regio
    Type: Application
    Filed: February 25, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Osamu Takata
  • Patent number: 8860486
    Abstract: According to one embodiment, a semiconductor device has a transistor comprising a source electrode, a drain electrode, and a gate electrode, a diode and a switch element connected in series between the gate and source electrodes of the transistor, and a control circuit configured to supply a control signal for switching the switch element. The control circuit has a predetermined time constant and is configured to supply the control signal to the switch element if a pulse signal having a voltage that is equal to or higher than a predetermined voltage is supplied to the gate electrode of the transistor.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Haruki, Osamu Takata
  • Publication number: 20140145780
    Abstract: According to one embodiment, a semiconductor device has a transistor comprising a source electrode, a drain electrode, and a gate electrode, a diode and a switch element connected in series between the gate and source electrodes of the transistor, and a control circuit configured to supply a control signal for switching the switch element. The control circuit has a predetermined time constant and is configured to supply the control signal to the switch element if a pulse signal having a voltage that is equal to or higher than a predetermined voltage is supplied to the gate electrode of the transistor.
    Type: Application
    Filed: June 11, 2013
    Publication date: May 29, 2014
    Inventors: Satoshi HARUKI, Osamu TAKATA
  • Patent number: 8519451
    Abstract: According to one embodiment, a semiconductor device includes a source region having p-type conductivity, a drain region having p-type conductivity, a channel region provided between the source region and the drain region and having n-type conductivity, a lower gate insulating film provided on the channel region, a lower gate electrode provided on the lower gate insulating film, an upper gate insulating film provided on the lower gate electrode, an upper gate electrode provided on the upper gate insulating film, and a switching element connected between the lower gate electrode and the source region.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Takata