Abstract: To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a CPU detects mode setting information added to instruction code and outputs a clock control signal and a power supply voltage control signal to a clock controlling section and a power supply voltage controlling section, respectively. When a plurality of processing engines execute an instruction in parallel, clock signals with a frequency lower than a predetermined frequency and power supply voltages lower than a predetermined voltage are supplied. As a result, power consumption is reduced and the processing ability is maintained by the parallel execution.

Abstract: A CMOS circuit characteristic automatic adjustment apparatus includes a replica signal generation circuit for generating a replica signal capable of minimizing a drain voltage of an MOS transistor in a target circuit, a replica circuit for receiving the replica signal, voltage buffers for receiving respective drain voltages of MOS transistors in the target circuit and the replica circuit, respectively, MOS transistors for receiving respective output voltages of the voltage buffers, a comparison circuit for comparing respective sizes of currents flowing in the MOS transistors, respectively, and an adjustment circuit for adjusting, based on a comparison result, operation states of the target circuit and the replica circuit.

Abstract: A CMOS circuit characteristic automatic adjustment apparatus includes a replica signal generation circuit for generating a replica signal capable of minimizing a drain voltage of an MOS transistor in a target circuit, a replica circuit for receiving the replica signal, voltage buffers for receiving respective drain voltages of MOS transistors in the target circuit and the replica circuit, respectively, MOS transistors for receiving respective output voltages of the voltage buffers, a comparison circuit for comparing respective sizes of currents flowing in the MOS transistors, respectively, and an adjustment circuit for adjusting, based on a comparison result, operation states of the target circuit and the replica circuit.

Abstract: To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a CPU detects mode setting information added to instruction code and outputs a clock control signal and a power supply voltage control signal to a clock controlling section and a power supply voltage controlling section, respectively. When a plurality of processing engines execute an instruction in parallel, clock signals with a frequency lower than a predetermined frequency and power supply voltages lower than a predetermined voltage are supplied. As a result, power consumption is reduced and the processing ability is maintained by the parallel execution.

Abstract: An A/D converter guarantees high conversion precision and reduces power consumption not only in a standby state but in any other states. Therefore, a subtraction circuit is added to the A/D converter obtain a difference between a reference voltage and an analog signal, and an analog signal stored as a reference voltage is used. The difference is converted only by an A/D conversion unit for converting lower bits, and an operation mode for stopping the operation of an idle conversion unit is designed, thereby to perform an analog-to-digital converting operation.

Abstract: The invention discloses a PLL formed by a phase detector, a filter, three VCO's (VCO1, VCO2, and VCO3), a multiplexer, and a frequency divider. The VCO1, VCO2, and VCO3 have different mean frequencies, each oscillating at a frequency controlled according to the voltage value of a phase control signal from the filter. The multiplexer selects one of the VCO's which operate in parallel. If a pulse of a digital phase difference signal UP indicating that an internal signal is delayed in phase with respect to a reference signal is output twice in succession, or if a pulse of a digital phase difference signal DOWN indicating that an internal signal is advanced in phase with respect to a reference signal is output twice in succession, a counter makes the multiplexer change its current VCO selection via a shift register. Accordingly, high-speed PLL pulling is achievable even if a PLL frequency variable-range is expanded.