Abstract: In a two-stage inverter circuit including an inverter circuit constituted by first and second FETs and an inverter circuit constituted by two FETs, a source and a gate of a third FET are connected to a first power source and a second power source, respectively. A drain of the third FET is connected to a source of the first FET. A source and a gate of a fourth FET are connected to the first power source and the second power source, respectively. A drain of the fourth FET is connected to a source of a seventh FET. A gate of the seventh FET is connected to the second power source, and a drain of the seventh FET is connected to a back gates of the first, third, fourth, seventh and fifth FETs. The drain of the third FET is connected to the drain of the fourth FET.

Abstract: A process is disclosed for preparing a heterocyclic aldehyde by oxidizing a heterocyclic alcohol with high selectivity and high yield. Specifically, the heterocyclic aldehyde is prepared by reacting a heterocyclic compound having at least one hydroxymethyl group bonded to a carbon atom of a heterocyclic ring with a hypohalogenous acid salt in the presence of a base to oxidize the hydroxymethyl group, wherein reaction is conducted in the co-presence of a 2,2,6,6-tetramethylpiperidine-1-oxyl derivative having at least two 2,2,6,6-tetramethylpiperidine-1-oxyl-4-yl groups.

Abstract: An input/output circuit operable in input and output modes and including an input/output terminal, pull-up and pull-down output transistors, and first and second logic circuits operated in accordance with data and an enable signal. A control circuit maintains the pull-up output transistor in an inactivated state regardless of the voltage applied to the input/output terminal in the input mode. A switch circuit disconnects the first logic circuit from a power supply when an input signal having voltage higher than the power supply voltage of the power supply is input to the input/output terminal in the input mode. A back gate control circuit supplies back gates of P-channel MOS transistors in the first logic circuit and the switch circuit with back gate voltage having the same voltage as the input signal when the input signal is input in the input mode.

Abstract: In a semiconductor device in which an applying voltage higher than a power supply voltage VDD is inputted to a terminal BUS, when the voltage VBUS is less than a voltage of the power supply voltage VDD plus a threshold voltage Vthp, a voltage obtained by subtracting a threshold voltage Vthn from the power supply voltage VDD is applied to the gate terminal G4 and the PMOS transistor P4 becomes conductive. The power supply voltage VDD is supplied to the gate terminal G2 to turn the PMOS transistor P2 off. When the voltage VBUS is equal to or higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp, the voltage VBUS is supplied to the gate terminal G4 to turn the PMOS transistor P4 off, and the PMOS transistor P3 conducts and supplies the voltage VBUS to the gate terminal G2 to turn the PMOS transistor P4 off. The voltage level is correctly maintained without an undesirable leak current from the terminal BUS regardless of the applying voltage VBUS.

Abstract: A tolerant input circuit that functions stably regardless of fabrication differences without having to adjust the threshold value of an input circuit. The tolerant input circuit includes a step-down device configured by an N-channel MOS transistor connected between an input pad and the input circuit. Voltage from a power supply is supplied to the gate of the N-channel MOS transistor in the step-down device to decrease the voltage of a high voltage signal provided to the input pad to the voltage of the power supply or lower. The signal with decreased voltage is provided to the input circuit. The tolerant input circuit includes a back gate voltage control circuit for increasing back gate voltage of the N-channel MOS transistor in the step-down device when the input pad is provided with a high voltage signal.

Abstract: In a two-stage inverter circuit including an inverter circuit constituted by first and second FETs and an inverter circuit constituted by two FETs, a source and a gate of a third FET are connected to a first power source and a second power source, respectively. A drain of the third FET is connected to a source of the first FET. A source and a gate of a fourth FET are connected to the first power source and the second power source, respectively. A drain of the fourth FET is connected to a source of a seventh FET. A gate of the seventh FET is connected to the second power source, and a drain of the seventh FET is connected to a back gates of the first, third, fourth, seventh and fifth FETs. The drain of the third FET is connected to the drain of the fourth FET.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: In a semiconductor device in which an applying voltage higher than a power supply voltage VDD is inputted to a terminal BUS, when the voltage VBUS is less than a voltage of the power supply voltage VDD plus a threshold voltage Vthp, a voltage obtained by subtracting a threshold voltage Vthn from the power supply voltage VDD is applied to the gate terminal G4 and the PMOS transistor P4 becomes conductive. The power supply voltage VDD is supplied to the gate terminal G2 to turn the PMOS transistor P2 off. When the voltage VBUS is equal to or higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp, the voltage VBUS is supplied to the gate terminal G4 to turn the PMOS transistor P4 off, and the PMOS transistor P3 conducts and supplies the voltage VBUS to the gate terminal G2 to turn the PMOS transistor P4 off. The voltage level is correctly maintained without an undesirable leak current from the terminal BUS regardless of the applying voltage VBUS.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: The present invention provides a process for preparing a heterocyclic aldehyde by oxidizing a heterocyclic alcohol with high selectivity and high yield. Specifically, the heterocyclic aldehyde is prepared by reacting a heterocyclic compound having at least one hydroxymethyl group bonded to a carbon atom of a heterocyclic ring with a hypohalogenous acid salt in the presence of a base to oxidize the hydroxymethyl group, wherein reaction is conducted in the co-presence of a 2,2,6,6-tetramethylpiperidine-1-oxyl derivative having at least two 2,2,6,6-tetramethylpiperidine-1-oxyl-4-yl groups.

Abstract: In an input/output buffer circuit to which input signal voltage VBUS higher than power source voltage VDD is possibly inputted to an input/output terminal BUS, a gate terminal G3 is controlled by a signal in-phase to a input/output mode switching signal CNT outputted from a buffer circuit 5, and the power source voltage VDD is applied when it is an input mode. When the input signal voltage VBUS is lower than voltage obtained by applying threshold voltage Vthp of PMOS transistor to the power source voltage VDD (VBUS<VDD+Vthp), voltage obtained by subtracting threshold voltage Vthn of NMOS transistor from the power source voltage VDD is applied to a gate terminal G1 (VG1=VDD−Vthn). On condition that Vthn>Vthp, a PMOS transistor P1 gets conductive, whereby the power source voltage VDD is applied to a gate terminal G2 and PMOS transistor P2 is turned off. Thereby, an unnecessary current path is not formed.

Abstract: In an input/output buffer circuit to which input signal voltage VBUS higher than power source voltage VDD is possibly inputted to an input/output terminal BUS, a gate terminal G3 is controlled by a signal in-phase to a input/output mode switching signal CNT outputted from a buffer circuit 5, and the power source voltage VDD is applied when it is an input mode. When the input signal voltage VBUS is lower than voltage obtained by applying threshold voltage Vthp of PMOS transistor to the power source voltage VDD (VBUS<VDD+Vthp), voltage obtained by subtracting threshold voltage Vthn of NMOS transistor from the power source voltage VDD is applied to a gate terminal G1 (VG1=VDD−Vthn). On condition that Vthn>Vthp, a PMOS transistor P1 gets conductive, whereby the power source voltage VDD is applied to a gate terminal G2 and PMOS transistor P2 is turned off. Thereby, an unnecessary current path is not formed.

Abstract: An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

Abstract: A restraining device for limiting forward movement of an operator of a wheeled mechanical vehicle in case of a collision includes two restraining bars pivotally mounted at opposite sides of a seat and extending toward one another. The restraining bars are mounted so as to pivot in a vertical plane about axes which are parallel to each other and lie on opposite sides of the seat. The restraining bars are synchronized or interlocked so that when one bar is raised or lowered by the occupant of the seat the other bar is also moved. A lock or retention device on one side of the seat holds the restraining bars in the lowered or raised position after they have been positioned by the occupant. The vehicle may be a forklift or front end loader and the run controls and load controls of the vehicle are interlocked with the synchronizing mechanism so that the run and load controls cannot be operated when the restraining bars are not in the occupant restraining position.