Abstract: A semiconductor chip (2) includes a surface electrode (3). A conductive bonding member (8) includes first and second bonding members (8a,8b) provided on the surface electrode (3). A lead electrode (9) is bonded to a part of the surface electrode (3) via the first bonding member (8a) and has no contact with the second bonding member (8b). A signal wire (11) is bonded to the surface electrode (3). The second bonding member (8b) is arranged between the first bonding member (8a) and the signal wire (11). A thickness of the first bonding member (8a) is larger than a thickness of the second bonding member (8b).

Abstract: A semiconductor chip (6) is disposed on the insulation substrate (2). A lead frame (8) is bonded to an upper surface of the semiconductor chip (6). A sealing resin (12) covers the semiconductor chip (6), the insulation substrate (2), and the lead frame (8). A stress mitigation resin (13) having a lower elastic modulus than that of the sealing resin (12) is partially applied to an end of the lead frame (8).

Abstract: A semiconductor chip (2) includes a surface electrode (3). A conductive bonding member (8) includes first and second bonding members (8a,8b) provided on the surface electrode (3). A lead electrode (9) is bonded to a part of the surface electrode (3) via the first bonding member (8a) and has no contact with the second bonding member (8b). A signal wire (11) is bonded to the surface electrode (3). The second bonding member (8b) is arranged between the first bonding member (8a) and the signal wire (11). A thickness of the first bonding member (8a) is larger than a thickness of the second bonding member (8b).

Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).

Abstract: A semiconductor chip (6) is disposed on the insulation substrate (2). A lead frame (8) is bonded to an upper surface of the semiconductor chip (6). A sealing resin (12) covers the semiconductor chip (6), the insulation substrate (2), and the lead frame (8). A stress mitigation resin (13) having a lower elastic modulus than that of the sealing resin (12) is partially applied to an end of the lead frame (8).

Abstract: A plurality of semiconductor devices (4a-4f, 5a-5f) are provided on an upper surface of the conductive base plate (1) via an insulating substrate (2) and a conductive pattern (3a-3d). A plurality of fins (6) are provided on a lower surface of the conductive base plate (1). A heat dissipating base plate (7) is provided to tips of the plurality of fins (6). A cooler (8) having an inflow port (9a) and an outflow port (9b) in a bottom surface surrounds the plurality of fins (6) and the heat dissipating base plate (7). A partition (10) separates a space surrounded by the cooler (8) and the heat dissipating base plate (7) into an inflow-side space (11a) connected to the inflow port (9a) and an outflow-side space (11b) connected to the outflow port (9b). A first slit (12a) is provided in a central portion of the heat dissipating base plate (7). Second and third slits (12b,12c) are respectively provided on both sides of the heat dissipating base plate (7) along a direction from an inflow side to an outflow side.

Abstract: A plurality of semiconductor devices (4a-4f, 5a-5f) are provided on an upper surface of the conductive base plate (1) via an insulating substrate (2) and a conductive pattern (3a-3d). A plurality of fins (6) are provided on a lower surface of the conductive base plate (1). A heat dissipating base plate (7) is provided to tips of the plurality of fins (6). A cooler (8) having an inflow port (9a) and an outflow port (9b) in a bottom surface surrounds the plurality of fins (6) and the heat dissipating base plate (7). A partition (10) separates a space surrounded by the cooler (8) and the heat dissipating base plate (7) into an inflow-side space (11a) connected to the inflow port (9a) and an outflow-side space (11b) connected to the outflow port (9b). A first slit (12a) is provided in a central portion of the heat dissipating base plate (7). Second and third slits (12b,12c) are respectively provided on both sides of the heat dissipating base plate (7) along a direction from an inflow side to an outflow side.

Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).

Abstract: A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole.

Abstract: A power semiconductor device module includes a plurality of inverters, each having a first transistor and a second transistor that are interposed in series between a first potential and a second potential and that operate complementarily. The plurality of inverters are assembled into a module. Only one predetermined inverter of the plurality of inverters is configured to detect temperatures of the first and second transistors, and control terminals for detection of the temperatures of the first and second transistors protrude from sides of the module.

Abstract: A semiconductor device includes a semiconductor element, a base plate having an upper surface on which the semiconductor element is mounted, a cooling fin disposed on a lower surface of the base plate, a jacket disposed in a sealing manner on the lower surface of the base plate, the jacket surrounding the cooling fin, and a header partition wall formed separately from the jacket and fixed to the jacket on the lower side of the cooling fin in the jacket, the header partition wall forming a header and a flow path for causing a refrigerant flow to the cooling fin.

Abstract: First chip main surfaces of first semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the first semiconductor chips are bonded to a first electrode. First chip main surfaces of second semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the second semiconductor chips are bonded to a first electrode. A plurality of electrodes are provided by a lead frame. An insulating member is provided on a side opposite to the chips when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips when viewed from the first electrodes.

Abstract: A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.

Abstract: A semiconductor device includes a semiconductor element, a base plate having an upper surface on which the semiconductor element is mounted, a cooling fin disposed on a lower surface of the base plate, a jacket disposed in a sealing manner on the lower surface of the base plate, the jacket surrounding the cooling fin, and a header partition wall formed separately from the jacket and fixed to the jacket on the lower side of the cooling fin in the jacket, the header partition wall forming a header and a flow path for causing a refrigerant flow to the cooling fin.

Abstract: A power semiconductor device with improved productivity, reduced size and reduction of amounting area therefore is provided. In the provided power semiconductor device, an external terminal does not limit an increase in current. The power semiconductor device is sealed with transfer molding resin. In the power semiconductor device, a cylindrical external terminal communication section is arranged on a wiring pattern so as to be substantially perpendicular to the wiring pattern. An external terminal can be inserted and connected to the cylindrical external terminal communication section. The cylindrical external terminal communication section allows the inserted external terminal to be electrically connected to the wiring pattern. A taper is formed at, at least, one end of the cylindrical external terminal communication section, which one end is joined to the wiring pattern.

Abstract: A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole.

Abstract: A power semiconductor device module includes a plurality of inverters, each having a first transistor and a second transistor that are interposed in series between a first potential and a second potential and that operate complementarily. The plurality of inverters are assembled into a module. Only one predetermined inverter of the plurality of inverters is configured to detect temperatures of the first and second transistors, and control terminals for detection of the temperatures of the first and second transistors protrude from sides of the module.

Abstract: First chip main surfaces of first semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the first semiconductor chips are bonded to a first electrode. First chip main surfaces of second semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the second semiconductor chips are bonded to a first electrode. A plurality of electrodes are provided by a lead frame. An insulating member is provided on a side opposite to the chips when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips when viewed from the first electrodes.

Abstract: A power block includes an insulating substrate, a conductive pattern formed on the insulating substrate, a power semiconductor chip bonded onto the conductive pattern by lead-free solder, a plurality of electrodes electrically connected to the power semiconductor chip and extending upwardly away from the insulating substrate, and a transfer molding resin covering the conductive pattern, the lead-free solder, the power semiconductor chip, and the plurality of electrodes, wherein surfaces of the plurality of electrodes are exposed at an outer surface of the transfer molding resin and lie in the same plane as the outer surface, the outer surface being located directly above the conductive pattern.

Abstract: A power semiconductor device in which transfer molding resin seals: a metallic circuit substrate; a power semiconductor element joined to a wiring pattern; and a side surface of a cylindrical external terminal communication section provided on the wiring pattern and to which an external terminal can be inserted and connected. The cylindrical external terminal communication section is substantially perpendicular to a surface on which the wiring pattern is formed. An outer surface of a metal plate of the metallic circuit substrate and a top portion of the cylindrical external terminal communication section are exposed from the transfer molding resin. The transfer molding resin is not present within the cylindrical external terminal communication section.