Patents by Inventor Osamu Yamane
Osamu Yamane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11715194Abstract: An information processing apparatus has an acquisitor configured to acquire an entire area image obtained by capturing an entire area of a processing surface of a wafer including at least one defect, a training image selector configured to select, as a training image, a partial image including at least one defect from the entire area image, a model constructor configured to construct a calculation model of generating a label image obtained by extracting and binarizing the defect included in the partial image, and a learner configured to update a parameter of the calculation model based on a difference between the label image generated by inputting the training image to the calculation model and a reference label image obtained by extracting and binarizing the defect of the training image.Type: GrantFiled: March 3, 2021Date of Patent: August 1, 2023Assignee: Kioxia CorporationInventors: Youyang Ng, Bo Wang, Takuji Ohashi, Osamu Yamane, Takeshi Fujiwara
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Patent number: 11387131Abstract: An alignment apparatus according to one embodiment, includes: a first and a second stage; a first and a second detector; a first and a second moving mechanism; and a controller. The first and second stages are configured to respectively hold a first and a second semiconductor substrate on which a first and a second alignment mark are respectively disposed. The first and second moving mechanisms are configured to respectively move the first and second stages relatively to each other. The controller is configured to perform the following (a), (b). (a) The controller control the detectors and the moving mechanisms to cause the first detector to detect the second alignment mark and to cause the second detector to detect the first alignment mark. (b) The controller calculate a position deviation between the substrates in accordance with results of the detections.Type: GrantFiled: March 6, 2020Date of Patent: July 12, 2022Assignee: Kioxia CorporationInventors: Miki Toshima, Osamu Yamane
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Publication number: 20220202131Abstract: A shoe includes: an upper in which an upper middle foot portion covering a middle foot portion of a foot of a wearer, an upper rear foot portion covering a heel portion of the foot, and a foot insertion opening for inserting the foot are formed; a sole located below the upper; a first support member disposed below a medial longitudinal arch of the foot inside the upper and including a lateral foot side portion fixed to the upper or the sole; and a first pulling-up member connected to a medial foot side portion of the first support member and enabled to apply, to the first support member, force for pulling up the first support member in a direction toward the upper rear foot portion and away from the sole.Type: ApplicationFiled: December 22, 2021Publication date: June 30, 2022Applicant: ASICS CORPORATIONInventors: Ryo MATSUNAGA, Tatsuya ISHIKAWA, Osamu YAMANE, Seigo NAKAYA
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Publication number: 20220076398Abstract: An information processing apparatus has an acquisitor configured to acquire an entire area image obtained by capturing an entire area of a processing surface of a wafer including at least one defect, a training image selector configured to select, as a training image, a partial image including at least one defect from the entire area image, a model constructor configured to construct a calculation model of generating a label image obtained by extracting and binarizing the defect included in the partial image, and a learner configured to update a parameter of the calculation model based on a difference between the label image generated by inputting the training image to the calculation model and a reference label image obtained by extracting and binarizing the defect of the training image.Type: ApplicationFiled: March 3, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventors: Youyang NG, Bo WANG, Takuji OHASHI, Osamu YAMANE, Takeshi FUJIWARA
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Patent number: 10952494Abstract: An outsole is formed of a viscoelastic body containing a rubber component. This viscoelastic body has a loss factor measured by a dynamic viscoelasticity measurement under conditions of a temperature of 23° C., a frequency of 10 Hz, a static strain of 10%, and a dynamic strain of 7% being 0.17 or more, a storage elastic modulus measured by the dynamic viscoelasticity measurement being 5.7 MPa or less, and a ratio of a tensile stress at 300% elongation to a tensile stress at 100% elongation being 4.4 or more. Such outsole is excellent in wet grip performance and durability.Type: GrantFiled: April 19, 2017Date of Patent: March 23, 2021Inventors: Masanori Sakamoto, Yusuke Nishiura, Osamu Yamane, Kenichi Harano
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Publication number: 20210043488Abstract: An alignment apparatus according to one embodiment, includes: a first and a second stage; a first and a second detector; a first and a second moving mechanism; and a controller. The first and second stages are configured to respectively hold a first and a second semiconductor substrate on which a first and a second alignment mark are respectively disposed. The first and second moving mechanisms are configured to respectively move the first and second stages relatively to each other. The controller is configured to perform the following (a), (b). (a) The controller control the detectors and the moving mechanisms to cause the first detector to detect the second alignment mark and to cause the second detector to detect the first alignment mark. (b) The controller calculate a position deviation between the substrates in accordance with results of the detections.Type: ApplicationFiled: March 6, 2020Publication date: February 11, 2021Applicant: Kioxia CorporationInventors: Miki TOSHIMA, Osamu YAMANE
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Patent number: 10714897Abstract: A distributed feedback semiconductor laser of includes a semiconductor stacked body and a first electrode. The semiconductor stacked body includes a first layer, an active layer that is provided on the first layer and is configured to emit laser light by an intersubband optical transition, and a second layer that is provided on the active layer. The semiconductor stacked body has a first surface including a flat portion and a trench portion; the flat portion includes a front surface of the second layer; the trench portion reaches the first layer from the front surface; the flat portion includes a first region and a second region; the first region extends along a first straight line; the second region extends to be orthogonal to the first straight line; and the trench portion and the second region outside the first region form a diffraction grating having a prescribed pitch along the first straight line. The first electrode is provided in the first region.Type: GrantFiled: September 1, 2016Date of Patent: July 14, 2020Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Shinji Saito, Tsutomu Kakuno, Osamu Yamane, Akira Tsumura
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Publication number: 20200165146Abstract: An ion exchanging unit exchanging ions contained in water includes a container for storing a plurality of ion exchange resins, a water supplying path through which to supply water to the container, a pure water discharging path through which to discharge water which has been ion-exchanged by the ion exchange resins, from the container, and a flow suppressing portion suppressing flow of the ion exchange resins by pressing downward the ion exchange resins stored in the container from above. The flow suppressing portion includes a pressing member placed on an upper surface of the ion exchange resins, the pressing member following the ion exchange resins which shrink more in volume as the ion exchange resins are used longer and then moving downward.Type: ApplicationFiled: November 21, 2019Publication date: May 28, 2020Inventor: Osamu YAMANE
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Patent number: 10599056Abstract: According to one embodiment, in a position measuring method, alignment measurement in a light exposure process is executed by irradiating a first mark with light having a wavelength of ?1, with respect to a processing object that includes a first layer and a second layer stacked above a substrate and a resist applied on the second layer. The first mark is provided in the first layer and includes a plurality of segments arranged at a pitch smaller than a resolution limit given by light having the wavelength of ?1. Then, overlay measurement is executed by irradiating the first mark and a second mark with light having a wavelength of ?2 shorter than the wavelength of ?1. The second mark has been formed by performing a light exposure and development process to the resist, and includes a plurality of segments arranged at the pitch.Type: GrantFiled: January 31, 2019Date of Patent: March 24, 2020Assignee: Toshiba Memory CorporationInventors: Miki Toshima, Osamu Yamane, Yosuke Okamoto
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Publication number: 20200081357Abstract: According to one embodiment, in a position measuring method, alignment measurement in a light exposure process is executed by irradiating a first mark with light having a wavelength of ?1, with respect to a processing object that includes a first layer and a second layer stacked above a substrate and a resist applied on the second layer. The first mark is provided in the first layer and includes a plurality of segments arranged at a pitch smaller than a resolution limit given by light having the wavelength of ?1. Then, overlay measurement is executed by irradiating the first mark and a second mark with light having a wavelength of ?2 shorter than the wavelength of ?1. The second mark has been formed by performing a light exposure and development process to the resist, and includes a plurality of segments arranged at the pitch.Type: ApplicationFiled: January 31, 2019Publication date: March 12, 2020Applicant: Toshiba Memory CorporationInventors: Miki Toshima, Osamu Yamane, Yosuke Okamoto
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Publication number: 20190380431Abstract: An outsole is formed of a viscoelastic body containing a rubber component. This viscoelastic body has a loss factor measured by a dynamic viscoelasticity measurement under conditions of a temperature of 23° C., a frequency of 10 Hz, a static strain of 10%, and a dynamic strain of 7% being 0.17 or more, a storage elastic modulus measured by the dynamic viscoelasticity measurement being 5.7 MPa or less, and a ratio of a tensile stress at 300% elongation to a tensile stress at 100% elongation being 4.4 or more. Such outsole is excellent in wet grip performance and durability.Type: ApplicationFiled: April 19, 2017Publication date: December 19, 2019Inventors: Masanori Sakamoto, Yusuke Nishiura, Osamu Yamane, Kenichi Harano
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Patent number: 10290995Abstract: A terahertz quantum cascade laser device includes a substrate, q semiconductor stacked body and a first electrode. The semiconductor stacked body includes an active layer and a first clad layer. The active layer is provided on the substrate and is configured to emit infrared laser light by an intersubband optical transition. The first clad layer is provided on the active layer. A ridge waveguide is provided in the semiconductor stacked body. A first distributed feedback region and a second distributed feedback region are provided at an upper surface of the first clad layer to be separated from each other along an extension direction of the ridge waveguide. The first electrode is provided at the upper surface of the first clad layer. A planar size of the first distributed feedback region is smaller than a planar size of the second distributed feedback region.Type: GrantFiled: September 1, 2017Date of Patent: May 14, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Kakuno, Shinji Saito, Osamu Yamane
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Publication number: 20190081456Abstract: A semiconductor laser device includes an active layer, a first layer, and a surface metal film. Multiple quantum well layers are stacked in the active layer; and the active layer is configured to emit laser light of a terahertz wave by an intersubband transition. The first layer is provided on the active layer and includes a first surface in which multiple pits are provided to form a two-dimensional lattice. The surface metal film is provided on the first layer and includes multiple openings. Each of the pits is asymmetric with respect to a line parallel to a side of the lattice. The laser light passes through the multiple openings and is emitted in a direction substantially perpendicular to the active layer.Type: ApplicationFiled: September 2, 2016Publication date: March 14, 2019Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Osamu YAMANE, Shinji SAITO, Tsutomu KAKUNO, Kei KANEKO, Rei HASHIMOTO
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Publication number: 20190081454Abstract: A distributed feedback semiconductor laser of includes a semiconductor stacked body and a first electrode. The semiconductor stacked body includes a first layer, an active layer that is provided on the first layer and is configured to emit laser light by an intersubband optical transition, and a second layer that is provided on the active layer. The semiconductor stacked body has a first surface including a flat portion and a trench portion; the flat portion includes a front surface of the second layer; the trench portion reaches the first layer from the front surface; the flat portion includes a first region and a second region; the first region extends along a first straight line; the second region extends to be orthogonal to the first straight line; and the trench portion and the second region outside the first region form a diffraction grating having a prescribed pitch along the first straight line. The first electrode is provided in the first region.Type: ApplicationFiled: September 1, 2016Publication date: March 14, 2019Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinji SAITO, Tsutomu KAKUNO, Osamu YAMANE, Akira TSUMURA
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Publication number: 20180069374Abstract: A terahertz quantum cascade laser device includes a substrate, q semiconductor stacked body and a first electrode. The semiconductor stacked body includes an active layer and a first clad layer. The active layer is provided on the substrate and is configured to emit infrared laser light by an intersubband optical transition. The first clad layer is provided on the active layer. A ridge waveguide is provided in the semiconductor stacked body. A first distributed feedback region and a second distributed feedback region are provided at an upper surface of the first clad layer to be separated from each other along an extension direction of the ridge waveguide. The first electrode is provided at the upper surface of the first clad layer. A planar size of the first distributed feedback region is smaller than a planar size of the second distributed feedback region.Type: ApplicationFiled: September 1, 2017Publication date: March 8, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Tsutomu KAKUNO, Shinji SAITO, Osamu YAMANE
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Patent number: 9893493Abstract: A surface emitting quantum cascade laser includes an active layer, a first semiconductor layer, and first electrode. The active layer has a plurality of quantum well layers stacked therein. The active layer is capable of emitting laser light by inter-subband transition. The first semiconductor layer is provided on the active layer and having a first surface provided with a plurality of pits so as to constitute a two-dimensional lattice. The first electrode is provided on the first semiconductor layer and having a periodic opening. Each pit is asymmetric with respect to a line parallel to a side of the lattice. The laser light is emitted in a direction generally perpendicular to the active layer from a pit exposed to the opening.Type: GrantFiled: August 25, 2016Date of Patent: February 13, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Saito, Tsutomu Kakuno, Osamu Yamane, Akira Tsumura
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Publication number: 20170271849Abstract: A surface emitting quantum cascade laser includes an active layer, a first semiconductor layer, and first electrode. The active layer has a plurality of quantum well layers stacked therein. The active layer is capable of emitting laser light by inter-subband transition. The first semiconductor layer is provided on the active layer and having a first surface provided with a plurality of pits so as to constitute a two-dimensional lattice. The first electrode is provided on the first semiconductor layer and having a periodic opening. Each pit is asymmetric with respect to a line parallel to a side of the lattice. The laser light is emitted in a direction generally perpendicular to the active layer from a pit exposed to the opening.Type: ApplicationFiled: August 25, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shinji SAITO, Tsutomu KAKUNO, Osamu YAMANE, Akira TSUMURA
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Patent number: 9159726Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2.Type: GrantFiled: March 10, 2014Date of Patent: October 13, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Yamane, Yoshihiro Yanai, Hiromitsu Mashita
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Publication number: 20150262932Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer interconnection structure unit; a stacked body; a channel body layer; a memory film; a contact electrode. The multilayer interconnection structure unit is provided on the semiconductor substrate, and the multilayer interconnection structure unit has interconnections. The stacked body is provided on the multilayer interconnection structure unit, and each of electrode layers and each of first insulating layers are alternately arranged in the stacked body. The channel body layer extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the channel body layer and each of the electrode layers. And the contact electrode extends in the stacked body in the stacking direction, and the contact electrode electrically connects any one of the electrode layers and any one of the interconnection layers.Type: ApplicationFiled: June 12, 2014Publication date: September 17, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Osamu YAMANE, Tadashi IGUCHI, Hiromitsu MASHITA
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Publication number: 20150069568Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2.Type: ApplicationFiled: March 10, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Osamu Yamane, Yoshihiro Yanai, Hiromitsu Mashita