Abstract: An aspect of the disclosure includes a comparator circuit comprising: a master latch comprising a first amplifier circuit and a first latch circuit coupled to an output of the first amplifier circuit; a slave latch comprising a second amplifier circuit having an input coupled to the output of the first amplifier circuit, and a second latch circuit coupled to an output of the second amplifier circuit; and a hysteresis compensation circuit coupled to the output of the second amplifier circuit and configured to cause a first predetermined signal level shift of an output signal of the first amplifier circuit in response to a high signal level at the output of the second amplifier circuit, and configured to cause a second predetermined signal level shift of an output signal of the first amplifier circuit in response to a low signal level at the output of the second amplifier circuit.

Abstract: An aspect of the disclosure includes a comparator circuit comprising: a master latch comprising a first amplifier circuit and a first latch circuit coupled to an output of the first amplifier circuit; a slave latch comprising a second amplifier circuit having an input coupled to the output of the first amplifier circuit, and a second latch circuit coupled to an output of the second amplifier circuit; and a hysteresis compensation circuit coupled to the output of the second amplifier circuit and configured to cause a first predetermined signal level shift of an output signal of the first amplifier circuit in response to a high signal level at the output of the second amplifier circuit, and configured to cause a second predetermined signal level shift of an output signal of the first amplifier circuit in response to a low signal level at the output of the second amplifier circuit.

Abstract: Disclosed herein is circuitry that extends the charge-steering (CS) logic library with a 2:1 CS-multiplexor (MUX) cell that can be used in a tree fashion to compose a 2N:1 CS-MUX. Also presented is the integration of 2N:1 CS-MUX with conventional CMOS signals at a parallel input, and a current-mode driver at the serialized output. Also presented are a non-return-to-zero (NRZ) to RZ serializing transmitter, a charge-steering multiplexor (CSM) pre-driver, and a CSM transmitter.

Abstract: Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.

Abstract: Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.

Abstract: According to a first aspect of the present inventive concept there is provided an equalizer system comprising a decision feedback equalizer (DFE), the DFE comprising: a static comparator configured as a decision device of the DFE; and a feedback path comprising a set of filter taps including at least a first filter tap; wherein the static comparator presents hysteresis and wherein a tap coefficient of the first filter tap is set such that an input signal level of the static comparator is shifted to compensate for the hysteresis.