Abstract: A storage device is disclosed. The storage device may include storage for data and at least one Input/Output (I/O) queue for requests from at least one virtual machine (VM) on a host device. The storage device may support an I/O queue creation command to request the allocation of an I/O queue for a VM. The I/O queue creation command may include an LBA range attribute for a range of Logical Block Addresses (LBAs) to be associated with the I/O queue. The storage device may map the range of LBAs to a range of Physical Block Addresses (PBAs) in the storage.

Abstract: A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID), and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor.

Abstract: A Lightweight Bridge (LWB) is disclosed. The LWB may be a circuit. An endpoint of the LWB that may expose a plurality of Physical Functions (PFs) to a host. A root port of the LWB may connect to a device and determine the PFs and Virtual Functions (VFs) exposed by the device. An Application Layer-Endpoint (APP-EP) and an Application Layer-Root Port (APP-RP) may translate between the PFs exposed by the endpoint and the PFs/VFs exposed by the device. The APP-EP and the APP-RP may implement a mapping between the PFs exposed by the endpoint and the PFs/VFs exposed by the device.

Abstract: A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD) and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may include an external connector to enable the PCIe switch to communicate with a processor, at least one connector to enable the PCIe switch to communicate with the NVMe SSD, a Power Processing Unit (PPU) to configure the PCIe switch, and an Erasure Coding controller including circuitry to apply an Erasure Coding scheme to data stored on the NVMe SSD.

Abstract: According to some example embodiments, a method includes receiving, a first command from a host device; determining, if the first command is part of an association group of commands by determining a first value of a first parameter of the first command in an association context table entry is greater than zero, the first parameter including a total number of commands in the association group of commands; determining, a first value of a second parameter of the first command, the second parameter including a tag value identifying the association group of commands; decrementing, the first value of the first parameter of the first command in the association context table entry; determining, if the first value of the first parameter in the association context table entry is zero; and executing, an action indicated in a third parameter of the first command.

Abstract: A method of streaming between a storage device and a secondary device includes receiving, by the storage device, from the secondary device, a memory read request command including a memory address of the storage device corresponding to a stream identity, the stream identity being unique between the storage device and the secondary device; streaming, by the storage device, data between the storage device and the secondary device by transferring the data corresponding to the memory address of the storage device to the secondary device; determining, by the storage device, that the data requested by the secondary device in the memory read request command is transferred to the secondary device; and ending, by the storage device, the streaming between the storage device and the secondary device.

Abstract: A system includes a host device; a storage device including an embedded processor; and a bridge kernel device including a bridge kernel hardware and a bridge kernel firmware, wherein the bridge kernel device is configured to receive a plurality of arguments from the host device and transfer the plurality of arguments to the embedded processor for data processing.

Abstract: A Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic is disclosed. The PCIe switch may include an external connector to enable the PCIe switch to communicate with a processor and at least one connector to enable the PCIe switch to communicate with at least one storage device. The PCIe switch may include a Power Processing Unit (PPU) to handle configuration of the PCIe switch. The Erasure Coding logic may include an Erasure Coding Controller with circuitry to apply an Erasure Coding scheme to data stored on the storage device, and a snooping logic including circuitry to intercept a data transmission received at the PCIe switch and modify the data transmission responsive to the Erasure Coding scheme.

Abstract: A chassis is disclosed. The chassis may include a processor, a switch, and at least one storage device in communication with a remote processor. The storage device may support an active power mode and a low power mode. A response to a Keep Alive (KA) message may be sent to the remote processor on behalf of the storage device when the storage device is in low power mode.

Abstract: A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD), a Field Programmable Gate Array (FPGA) to implement one or more functions supporting the NVMe SSD, such as data acceleration, data deduplication, data integrity, data encryption, and data compression, and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may communicate with both the FPGA and the NVMe SSD.

Abstract: A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID), and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor.

Abstract: A Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic is disclosed. The PCIe switch may include an external connector to enable the PCIe switch to communicate with a processor and at least one connector to enable the PCIe switch to communicate with at least one storage device. The PCIe switch may include a Power Processing Unit (PPU) to handle configuration of the PCIe switch. The Erasure Coding logic may include an Erasure Coding Controller with circuitry to apply an Erasure Coding scheme to data stored on the storage device, and a snooping logic including circuitry to intercept a data transmission received at the PCIe switch and modify the data transmission responsive to the Erasure Coding scheme.

Abstract: A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD) and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may include an external connector to enable the PCIe switch to communicate with a processor, at least one connector to enable the PCIe switch to communicate with the NVMe SSD, a Power Processing Unit (PPU) to configure the PCIe switch, and an Erasure Coding controller including circuitry to apply an Erasure Coding scheme to data stored on the NVMe SSD.

Abstract: Embodiments of the present invention include a drive-to-drive storage system comprising a host server having a host CPU and a host storage drive, one or more remote storage drives, and a peer-to-peer link connecting the host storage drive to the one or more remote storage drives. The host storage drive includes a processor and a memory, wherein the memory has stored thereon instructions that, when executed by the processor, causes the processor to transfer data from the host storage drive via the peer-to-peer link to the one or more remote storage drives when the host CPU issues a write command.

Abstract: A system and method for supporting data protection across field programmable gate array (FPGA) solid state drives (SSDs) includes a storage system having a first group of solid state drives connected to a FPGA. The FPGA includes a first data protection controller configured to manage input/output requests to and from the first group of solid state disks according to a data protection configuration, generate parity bits according to the data protection configuration, and store the parity bits on at least parity solid state drive from the first group of solid state drives.

Abstract: According to some example embodiments, a method includes receiving, a first command from a host device; determining, if the first command is part of an association group of commands by determining a first value of a first parameter of the first command in an association context table entry is greater than zero, the first parameter including a total number of commands in the association group of commands; determining, a first value of a second parameter of the first command, the second parameter including a tag value identifying the association group of commands; decrementing, the first value of the first parameter of the first command in the association context table entry; determining, if the first value of the first parameter in the association context table entry is zero; and executing, an action indicated in a third parameter of the first command.

Abstract: A storage device is disclosed. The storage device may include storage for data and at least one Input/Output (I/O) queue for requests from at least one virtual machine (VM) on a host device. The storage device may support an I/O queue creation command to request the allocation of an I/O queue for a VM. The I/O queue creation command may include an LBA range attribute for a range of Logical Block Addresses (LBAs) to be associated with the I/O queue. The storage device may map the range of LBAs to a range of Physical Block Addresses (PBAs) in the storage.

Abstract: A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.

Abstract: A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.

Abstract: A mechanism is provided at a host system to allow multiple entities (clients) to send and receive messages of a particular class of management services in a switched fabric for scalable solutions.