Patents by Inventor Oscar R. Mitchell

Oscar R. Mitchell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7913261
    Abstract: An information-processing method for application-specific processing of messages. A message is received. Whether the message is in a selected application format is ascertained. If not, the message is routed to a next location. If so, the message is routed to a selected application processor, processed by the processor, and routed to the next location.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: March 22, 2011
    Assignee: nCipher Corporation, Ltd.
    Inventors: Oscar R. Mitchell, Robert Bradford Cohen, Eleanor Coy, Rajat Datta, Randall Findley, James Garrett, Richard Goble, Greg North, Daniel Reents, Leslie Zsohar
  • Patent number: 7900042
    Abstract: A method, system, and device for encrypted packet inspection allowing an authorized third party device to monitor cryptographic handshaking information (full- duplex) between two other devices and together with the secret private key then transparently decrypt the bulk encrypted data stream. The scope of this invention encompasses many applications, three examples of which are firewalls, load balancers, and local network caches. Additionally, this invention achieves and contributes to the efficient handling of encrypted information in other ways, three examples of which are making switching, routing, and security decisions.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: March 1, 2011
    Assignee: nCipher Corporation Limited
    Inventors: Rick Hall, Oscar R. Mitchell
  • Publication number: 20030072442
    Abstract: A method, software, and device for encrypting data, exchanging keys, and processing data that includes exponentiating by iteratively cisponentiating according to cisponentiator C(G, E, B, R, m)=GEBR mod m, wherein G is a fleeting multiplicand base, E is an enduring cisponent, B is a recurring multiplier, R is an enduring factor, and m is a persistent modulus. E may be a fixed characteristic of the cisponentiator. E may also be a power of 2. R may be fixed. In one of many possible combinations, E is a fixed characteristic of the cisponentiator, while R is fixed. In that case also, E may be a power of 2. Modulus m may be fixed. In one of many possible combinations, E is a fixed characteristic of the cisponentiator, R is fixed, and m is fixed. As one of many alternatives, data may be encrypted using asymmetric encryption.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 17, 2003
    Inventors: George Robert Blakley, Rajat Datta, Oscar R. Mitchell, Kyle Stein
  • Publication number: 20030018891
    Abstract: A method, system, and device for encrypted packet inspection allowing an authorized third party device to monitor cryptographic handshaking information (full-duplex) between two other devices and together with the secret private key then transparently decrypt the bulk encrypted data stream.
    Type: Application
    Filed: June 7, 2002
    Publication date: January 23, 2003
    Inventors: Rick Hall, Oscar R. Mitchell
  • Publication number: 20020191604
    Abstract: An information-processing method for application-specific processing of messages. A message is received. Whether the message is in a selected application format is ascertained. If not, the message is routed to a next location. If so, the message is routed to a selected application processor, processed by the processor, and routed to the next location.
    Type: Application
    Filed: February 5, 2002
    Publication date: December 19, 2002
    Inventors: Oscar R. Mitchell, Robert Bradford Cohen, Eleanor Coy, Rajat Datta, Randall Findley, James Garrett, Richard Goble, Greg North, Daniel Reents, Leslie Zsohar
  • Patent number: 5555543
    Abstract: A computer networking system includes a cross bar switch and a protocol for operating the same. The crossbar switch typically connects a plurality of ports one to another and the protocol establishes a connection between a first desired port and a second desired port selected from the plurality of ports. Each port further connects to a compute element via a master bidirectional bus and a slave bidirectional bus. Any of the compute elements can serve as either a master or slave to any other compute element connected to the crossbar switch. A master port connects the bidirectional bus to the crossbar switch and a slave port connects the slave bidirectional bus to the crossbar switch. The master port is reserved for compute element initiated operations while the slave port is reserved for network initiated operations.
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: September 10, 1996
    Assignee: International Business Machines Corporation
    Inventors: Gregory F. Grohoski, Oscar R. Mitchell, Tung M. Nguyen, Yongjae Rim
  • Patent number: 5448716
    Abstract: An architecture and method for booting a multi-processor system having processor local memory and shared global memory, with shared global memory access managed by an atomic memory access controller and cache coherence managed by software. Reset circuits are used to synchronize to a master clock a commonly distributed start signal and processor individualized restart sequences, which reset circuit signals are distributed to reset both local and global memory. Global memory testing is assigned to a processor based upon its rate status in completing an internal test sequence. The systems and methods are particularly suited to booting a group of multiple but relatively independent processors. Furthermore, the practice of the invention facilitates booting of such system when one or more of the processors have been disconnected or failed.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: September 5, 1995
    Assignee: International Business Machines Corporation
    Inventors: William R. Hardell, Jr., James D. Henson, Jr., Oscar R. Mitchell
  • Patent number: 5327548
    Abstract: A system and method for managing spare bit steering information in a multi-processor system having a global/local memory architecture. During the system boot cycle one of the multiple processors is selected to test global memory and to configure the steering of the spare bits by bank or the like. Each processor tests its own local memory and defines the associated spare bit steering for the local memory. The global memory spare bit steering configuration information, as well as other global memory configuration information, in the selected processor is distributed to the other processors using registers in a commonly accessible atomic semaphore controller or through a commonly accessible block of global memory. Preferably, the selection of the processor to test the global memory is performed so that no single processor always has the responsibility. In this way, the acquisition of global memory spare bit steering information is not linked to the operative status of any one processor.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: July 5, 1994
    Assignee: International Business Machines Corporation
    Inventors: William R. Hardell, Jr., James D. Henson, Jr., Oscar R. Mitchell