Patents by Inventor OSCAR ROSELL
OSCAR ROSELL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240103876Abstract: Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.Type: ApplicationFiled: November 7, 2023Publication date: March 28, 2024Inventors: Ishwar AGARWAL, George CHRYSOS, Oscar ROSELL MARTINEZ, Yevgeniy BAK
-
Patent number: 11847459Abstract: Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.Type: GrantFiled: April 12, 2022Date of Patent: December 19, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Ishwar Agarwal, George Chrysos, Oscar Rosell Martinez, Yevgeniy Bak
-
Publication number: 20230325191Abstract: Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.Type: ApplicationFiled: April 12, 2022Publication date: October 12, 2023Inventors: Ishwar AGARWAL, George CHRYSOS, Oscar ROSELL MARTINEZ, Yevgeniy BAK
-
Publication number: 20230143375Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.Type: ApplicationFiled: January 13, 2023Publication date: May 11, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Ishwar AGARWAL, George Zacharias CHRYSOS, Oscar ROSELL MARTINEZ
-
Patent number: 11599415Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.Type: GrantFiled: July 9, 2021Date of Patent: March 7, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
-
Publication number: 20230020131Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.Type: ApplicationFiled: July 9, 2021Publication date: January 19, 2023Inventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
-
Publication number: 20220414001Abstract: Techniques of memory inclusivity management are disclosed herein. One example technique includes receiving a request from a core of the CPU to write a block of data corresponding to a first cacheline to a swap buffer at a memory. In response to the request, the method can include retrieving metadata corresponding to the first cacheline that includes a bit encoding a status value indicating whether the memory block at the memory currently contains data of the first cacheline or data corresponding to a second cacheline. The first and second cachelines alternately sharing the swap buffer at the memory. When the decoded status value indicates that the memory block at the first memory currently contains the data corresponding to the first cacheline, an instruction is transmitted to the memory controller to directly write the block of data to the memory block at the first memory.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
-
Patent number: 11321171Abstract: Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory, data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.Type: GrantFiled: May 24, 2021Date of Patent: May 3, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Ishwar Agarwal, George Zacharias Chrysos, Oscar Rosell Martinez
-
Patent number: 11218139Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.Type: GrantFiled: May 14, 2020Date of Patent: January 4, 2022Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Clint Wayne Mumford, Kshitiz Saxena, Miguel Comparan, Adam Muff, Oscar Rosell
-
Publication number: 20210359672Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.Type: ApplicationFiled: May 14, 2020Publication date: November 18, 2021Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: CLINT WAYNE MUMFORD, KSHITIZ SAXENA, MIGUEL COMPARAN, ADAM MUFF, OSCAR ROSELL