Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack. A semiconductor device is provided. The semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack, where the tunneling barrier comprises a center portion and two outer portions, where the center portion is on an upper horizontal portion of the reference layer, and the two outer portions are on a slanted upper surface of an encapsulation layer surrounding the reference layer. Forming a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack.

Abstract: A semiconductor structure including a metal sidewall spacer arranged on a vertical sidewall of a dielectric pedestal, a fuse dielectric layer on top of the dielectric pedestal, and a conductive element on top of the fuse dielectric layer and directly above the metal sidewall spacer.

Abstract: A magnetic tunnel junction pillar is positioned above a bottom electrode composed of a metal-oxide region in contact with a first portion of the magnetic tunnel junction pillar and a metal region surrounding the metal-oxide region. A sidewall spacer is positioned along sidewalls of the magnetic tunnel junction pillar, and the metal region is in contact with a bottom surface of the sidewall spacer and a second portion of the magnetic tunnel junction pillar.

Abstract: A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode, a magnetic tunnel junction (MTJ) and a top electrode disposed on the MTJ. The MTJ has a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. The bottom electrode and the top electrode are recessed within a periphery of the MTJ to form a disrupted sidewall profile.

Abstract: A semiconductor device is provided. The semiconductor device includes a base layer, a first MRAM device formed on the base layer, and a second MRAM device formed on the base layer. The first MRAM device has a different performance characteristic than the second MRAM device.

Abstract: A magnetoresistive random access memory (MRAM) includes a first conductor and a magnetic tunnel junction (MTJ) having a bottom electrode. An anchor via connects the first conductor to the bottom electrode. The anchor via includes a via conductor encapsulated within a diffusion barrier. The diffusion barrier includes a conductive cap disposed between the via conductor and the bottom electrode.

Abstract: A semiconductor device includes a metal line having a longitudinal axis. The metal line includes a first segment extending in a direction of the longitudinal axis and having a first cross-section, the first cross-section including a wider side and a narrower side. A second segment extends in a direction of the longitudinal axis and has a second cross-section, the second cross-section including a wider side and a narrower side. The narrower side of the second segment is formed in contact with the wider side of the first segment such that a portion of the wider side of the first segment extends beyond the narrow side of the second segment to form a terrace and the terrace and a tapered sidewall of the second segment form an acute angle.

Abstract: According to the embodiment of the present invention, a semiconductor device includes an interconnect. The interconnect includes a bottom interconnect section and a top interconnect section. The bottom interconnect section includes a first orientation along a Y-axis. The top interconnect section is coupled to the bottom interconnect section and includes a second orientation along to the Y-axis. The second orientation of the top interconnect section is a vertical reflection of the first orientation of the bottom interconnect section.

Abstract: Memory structures including an MTJ-containing pillar that is void of re-sputtered bottom electrode metal particles is provided by first forming the MTJ-containing pillar on a sacrificial material-containing structure, and thereafter replacing the sacrificial material-containing structure with at least a replacement bottom electrode structure. In some embodiments, the sacrificial material-containing structure is replaced with both a bottom electrode diffusion barrier liner and a replacement bottom electrode structure.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the stack includes a hexagonal profile. A semiconductor device including a lower word line, a magnetic tunnel junction (MTJ) stack, where a cross section of a first electrode of the MTJ stack comprises a hexagonal profile. A method including forming a bottom electrode, the bottom electrode includes a side surface including a width at a middle section of the bottom electrode greater than a width at a lower surface of the bottom electrode, and the width at the middle section of the bottom electrode greater than a width at an upper surface of the bottom electrode.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the MTJ stack comprises a trapezoid profile. A semiconductor device including a lower word line and a first electrode above and connected to the lower word line, where a cross section of an electrode includes a trapezoid profile. A method including forming a bottom electrode, the bottom electrode includes a tapered side surface including a width at an upper surface of the bottom electrode less than a width at a lower surface of the bottom electrode.

Abstract: A semiconductor structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a third region vertically aligned above a second region vertically aligned above a first region, the third region includes three sections: an upper section including a first width; a middle section including an upper horizontal surface including the first width and a lower horizontal surface including a second width; and a lower section including the second width; where the first width is less than the second width; and the second region including a third width at an upper horizontal surface of the second region and a fourth width at a lower horizontal surface of the second region, where the third width is greater than the fourth width.

Abstract: A semiconductor structure comprises a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter, a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter, and an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter. At least two of the first diameter, the second diameter and the third diameter are different.

Abstract: Embodiments of present invention provide a wiring structure. The wiring structure includes a metal line in a dielectric layer, where the metal line has a first sidewall and a second sidewall opposite the first sidewall and, from a bottom to a top thereof, includes at least a first section and a second section, where first and second sidewalls of the first section lean outwards from a bottom to a top of the first section, and first and second sidewalls of the second section lean inwards from a bottom to a top of the second section. A method of manufacturing the wiring structure is also provided.

Abstract: A structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a first region and a second region one above another, where the first region comprises a width which increases relative to height, and where the second region comprises a width which decreases relative to height.

Abstract: A semiconductor structure that includes: a plurality of metal wires, and at least one dielectric substrate surrounding the plurality of metal wires. Each of the plurality of metal wires includes a tapered upper portion, a tapered lower portion, and a middle portion between the tapered upper portion and the tapered lower portion that is wider than the tapered upper and lower portions.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a dielectric layer on top of a bottom contact; creating an opening in the dielectric layer, the opening has a slant top edge; filling a bottom portion of the opening to form a bottom electrode; filling a top portion of the opening with a first ferromagnetic material to form a first ferromagnetic layer; forming a stack of blanket layers, including a blanket tunnel barrier layer, a blanket second ferromagnetic layer, and a blanket top electrode layer, on top of the first ferromagnetic layer; patterning the stack of blanket layers into a top portion of a magnetic tunnel junction stack that includes a tunnel barrier layer, a second ferromagnetic layer, and a top electrode; and forming a top contact in contact with the top electrode. A structure formed thereby is also provided.