Abstract: Apparatus and methods for reducing crosstalk in personal audio equipment are provided. In an example, a method to reduce headset audio crosstalk can include applying a first signal to a first speaker channel of a headset, coupling a second speaker channel to a first input of a comparator of a crosstalk compensation circuit using a first switch of the crosstalk compensation circuit, the switch and detect circuit including the crosstalk compensation circuit, coupling a first resistor divider to a second input of the comparator using a second switch of the crosstalk compensation circuit, and adjusting a resistance setting of the first resistor divider from an initial setting using an output of the comparator.

Abstract: Apparatus and methods for reducing crosstalk in personal audio equipment are provided. In an example, a method to reduce headset audio crosstalk can include applying a first signal to a first speaker channel of a headset, coupling a second speaker channel to a first input of a comparator of a crosstalk compensation circuit using a first switch of the crosstalk compensation circuit, the switch and detect circuit including the crosstalk compensation circuit, coupling a first resistor divider to a second input of the comparator using a second switch of the crosstalk compensation circuit, and adjusting a resistance setting of the first resistor divider from an initial setting using an output of the comparator.

Abstract: Method and apparatus, among other things, are provided for detecting a charger type. In an example, a method to classify a potential charger coupled to a port of an electronic device can include detecting the potential charger coupled to a USB-compatible port of the electronic device, applying a pull-down current to first and second data lines of the USB-compatible port to provide a first test voltage on each of the first and second data lines, and executing a primary detection process of a USB Battery Charging 1.2 Compliance Plan if the first test voltage on each of the first and second data lines is not between a first threshold and a second threshold using the pull-down current.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: A fuel gauge can include a resistor configured to generate predetermined temperature information and a switch configured to couple a temperature sensor to a temperature output of the fuel gauge in a first state and to couple the resistor to the temperature output of the fuel gauge in a second state.

Abstract: Method and apparatus, among other things, are provided for detecting a charger type. In an example, a method to classify a potential charger coupled to a port of an electronic device can include detecting the potential charger coupled to a USB-compatible port of the electronic device, applying a pull-down current to first and second data lines of the USB-compatible port to provide a first test voltage on each of the first and second data lines, and executing a primary detection process of a USB Battery Charging 1.2 Compliance Plan if the first test voltage on each of the first and second data lines is not between a first threshold and a second threshold using the pull-down current.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: An MIPI controller using undefined or unknown MIPI LP codes to select among several destinations is disclosed. The codes may be intercepted and decoded to select among analog switches that, in one illustrative embodiment, connects the MIPI clock and data signals to a first or a second or to both displays of a mobile phone. In other applications additional destinations may also be selected.

Abstract: An apparatus and method are described for sending serialized command in an environment where ESD or other phenomenon might cause malfunctions. Commands are encoded where there are at least two bit changes between any two commands. In this example, each command code that is different from legal commands by only one bit is an illegal command, Illustratively, if six bits provide 64 codes for commands, and only eight codes are used for legal commands, there will be 56 illegal command codes. Illustratively, any command code, that is only one bit different from a legal command, will be an illegal command. In practice a illegal command may be detected, and the system may recover. An illegal command due to and ESD event may be defined, and when detected a recovery process may be entered. When data (not command) are being sent, error detecting and correcting bits may be employed.

Abstract: A serializing/deserializing interface is discussed for reducing the number of connections and signals being carried over a flex cable as would be found in a hand held mobile device. In particular the interface interleaves data, multiplexes data and multiplexes control for a number of I/O devices. For example those I/O devices might include an LCD display, a camera, a keypad and a GPIO (general purpose I/O) device.

Abstract: A transceiver driver for shaping an output signal includes one or more capacitive elements designed to manipulate the current applied to the control node of the driver's output transistor. The capacitive elements may be one or more capacitors coupled to an inverter branch that provides turn-on and turn-off potential to the gate of the output transistor. The capacitive elements act to charge or discharge the transistor's gate gradual in a highly programmable way so as to make the driver substantially independent of fabrication, supply voltage, and operating temperature vagaries.

Abstract: A transceiver driver for shaping an output signal includes one or more capacitive elements designed to manipulate the current applied to the control node of the driver's output transistor. The capacitive elements may be one or more capacitors coupled to an inverter branch that provides turn-on and turn-off potential to the gate of the output transistor. The capacitive elements act to charge or discharge the transistor's gate gradual in a highly programmable way so as to make the driver substantially independent of fabrication, supply voltage, and operating temperature vagaries.

Abstract: A mid-connect structure having on one side a first set of function cards in parallel with one another and having a plurality of mid-connect elements applied thereto, and having on the other side a second set of function cards in parallel with one another and having a plurality of mid-connect elements applied thereto. The first set of function cards are electrically coupled to the second set of function cards by connecting the mid-connect elements of the first set to corresponding mid-connect elements of the second set. The first set of function cards are oriented at an angle other than parallel relative to the second set of function cards, thereby allowing one or more function cards on one side to be electrically coupled to one or more function cards on the other side. Typically, this would be a perpendicular arrangement of the first set relative to the second set.

Abstract: A CMOS-based circuit for translating a differential-input into a single-ended output capable of driving large loads with little or no compromise in speed. This translator provides a symmetric single-ended output signal capable of driving a wide range of loads with minimal distortion. In contrast to earlier such translators, the circuit of the present invention ensures that the output signal is coupled directly to the high-voltage rail after being switched to logic HIGH and that that coupling remains in effect until an input signal causing the output to switch to logic LOW is received. Similarly, when the output signal is switched to logic LOW, it is coupled directly to the low-voltage rail of the circuit and left so coupled until it is affirmatively switched to logic HIGH. This feature ensures that regardless of load, the output signal completely switches to the proper logic stage.

Abstract: A multiplexer for selecting a single output signal from a plurality of input signals. For a plurality of complementary input signal pairs in particular, the multiplexer includes for each pair of complementary input signals a control sub-circuit having a selection switch and a common resistance in parallel. The switch and the common resistance have a common low-potential node that is tied to a pair of resistances that are in parallel, wherein each of the parallel resistances is coupled to the respective high-potential nodes of a differential amplifier. A particular pair of incoming complementary input signal pairs controls the differential amplifier. An off-circuit selection signal selects which switch of a plurality of control sub-circuits is activated. When a switch is on, it creates a bypassing of the common resistance, thereby enabling the turn-on of output drivers coupled to the differential amplifier.

Abstract: A pointer processor circuit substantially eliminates the pointer gap during justification of an outgoing SONET/SDH frame relative to an incoming SONET/SDH frame. The pointer interpreter circuit PI is constructed to receive an incoming frame, interpret the pointer H1H2, and write data payload bytes of the incoming frame into a FIFO memory. An input clock CLK1 controls the writing of data payload bytes into the FIFO. The FIFO stores only data bytes. A pointer generator circuit PG is coupled to the FIFO and is constructed to read out data payload bytes from the FIFO, create an outgoing frame, and calculate a new pointer. An output clock CLK2 controls reading of data from the FIFO to form an outgoing frame. The PI, FIFO and PG cooperate for justification of the outgoing frame relative to the incoming frame.

Abstract: A pointer processing circuit processes SONET/SDH frames and calculates a new pointer value. A pointer interpreter circuit (PI) is constructed to receive an incoming frame, identify the pointer in transport overhead bytes of the frame, interpret the pointer, and send the pointer value directly to a pointer generator circuit (PG). The pointer value indicates the position of the first byte of the data payload bytes of the incoming frame starting at the trace byte J1. The PI is constructed to tag the next data byte after the pointer H1 H2 and negative justification data holding byte location H3 and send the tagged data byte directly to a FIFO without the delay of counting down to the trace byte J1 of the incoming frame. A first in first out memory FIFO is coupled to the PI for writing data payload bytes from the incoming frame into the FIFO. A pointer generator circuit (PG) is coupled to the FIFO for changing the pointer on the outgoing frame.

Abstract: A temperature compensated ECL output driver circuit incorporates an ECL output gate (Q4,Q3) coupled between high (V.sub.CC) and low (V.sub.EE) potential power rails with output voltage swing resistors (R2, R1). The ECL output gate provides an output node (N1) at the collector node of one of the ECL output gate transistors (Q4). A first current sink (Q5,R4) is coupled between the common emitter node coupling (N3) of the ECL output gate (Q4,Q3) and low potential power rail (V.sub.EE). A compensating current source (Q11,R5) is coupled to the ECL output gate output node (N1) for generating a supplementary compensating current during operation of the ECL output driver circuit in intermediate and high temperature operating ranges. A compensating current switch (Q9,Q10) is coupled in the compensating current path and is constructed for switching off the supplementary compensating current in a specified low temperature operating range to maintain the logic high output signal V.sub.OH within specifications.