Patents by Inventor Osher Yifrach
Osher Yifrach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11269651Abstract: A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.Type: GrantFiled: September 10, 2019Date of Patent: March 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Klein, Nicol Hofmann, Cedric Lichtenau, Osher Yifrach
-
Publication number: 20210073000Abstract: A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.Type: ApplicationFiled: September 10, 2019Publication date: March 11, 2021Inventors: MICHAEL KLEIN, NICOL HOFMANN, CEDRIC LICHTENAU, OSHER YIFRACH
-
Patent number: 10614183Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: GrantFiled: December 29, 2017Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
-
Patent number: 10606971Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.Type: GrantFiled: November 29, 2017Date of Patent: March 31, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Shlomit Koyfman, Shiri Moran, Ido Rozenberg, Osher Yifrach
-
Patent number: 10585995Abstract: Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: GrantFiled: June 26, 2017Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
-
Patent number: 10572624Abstract: A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.Type: GrantFiled: April 30, 2018Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Erez Barak, Shlomit Koyfman, Eyal Naor, Ziv Nevo, Osher Yifrach
-
Publication number: 20190332741Abstract: A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: EREZ BARAK, Shlomit Koyfman, Eyal Naor, Ziv Nevo, Osher Yifrach
-
Patent number: 10324816Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: GrantFiled: March 8, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
-
Patent number: 10318395Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: GrantFiled: November 13, 2017Date of Patent: June 11, 2019Assignee: INTERNATION BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
-
Publication number: 20190163600Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Inventors: EREZ BARAK, SHLOMIT KOYFMAN, SHIRI MORAN, IDO ROZENBERG, OSHER YIFRACH
-
Patent number: 10296687Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: GrantFiled: February 23, 2018Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
-
Publication number: 20180373611Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: ApplicationFiled: December 29, 2017Publication date: December 27, 2018Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
-
Publication number: 20180373610Abstract: Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: ApplicationFiled: June 26, 2017Publication date: December 27, 2018Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
-
Publication number: 20180373828Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: ApplicationFiled: February 23, 2018Publication date: December 27, 2018Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
-
Publication number: 20180260308Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: ApplicationFiled: March 8, 2017Publication date: September 13, 2018Inventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
-
Publication number: 20180260311Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: ApplicationFiled: November 13, 2017Publication date: September 13, 2018Inventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach