Abstract: A method is performed at a FPGA coprocessor having memory that stores a plurality of blocks of compressed seismic traces. The method includes: receiving, from a host, a request for processing a predefined set of seismic traces, the request including block location and trace header information; accessing one or more of the blocks of compressed seismic traces from the memory in accordance with the block location information; decompressing each of the one or more accessed blocks into one or more seismic traces thereby forming a plurality of decompressed traces of seismic data; selecting all or a portion of the decompressed traces of seismic data in accordance with the trace header information; processing the selected decompressed traces of seismic data by applying one or more predefined operations to the seismic data; and returning the processed seismic data to the host.

Abstract: A plurality of hardware cells are defined, wherein at least a given one of the hardware cells corresponds to sets of vertices from a graph having vertices and edges interconnecting the vertices, and each of the sets are from a corresponding one of a number of portions of the graph. The given hardware cell is adapted to select one of the sets of vertices and to define for the selected set of vertices whether an edge exists in the graph between the vertices in the selected set. The hardware cells are used to analyze one or more properties of the graph, such as reachability or shortest path. The graph is mapped into an adjacency matrix, which contains a number of contexts, each context having a number of elements, and where the given hardware cell corresponds to multiple contexts of the adjacency matrix.

Abstract: A plurality of hardware cells are defined, wherein at least a given one of the hardware cells corresponds to sets of vertices from a graph having vertices and edges interconnecting the vertices, and each of the sets are from a corresponding one of a number of portions of the graph. The given hardware cell is adapted to select one of the sets of vertices and to define for the selected set of vertices whether an edge exists in the graph between the vertices in the selected set. The hardware cells are used to analyze one or more properties of the graph, such as reachability or shortest path. The graph is mapped into an adjacency matrix, which contains a number of contexts, each context having a number of elements, and where the given hardware cell corresponds to multiple contexts of the adjacency matrix.