Abstract: A method estimates source resistance for a transistor. A substrate region under a gate for the transistor is modeled as a gate region having a uniform resistivity .rho..sub.g. A source of the transistor is modeled as a source region having a uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s1 are used to calculate a first current from the source of the transistor to a drain of the transistor. The source of the transistor is then modeled as a source region having another uniform resistivity .rho..sub.s2. The uniform resistivity .rho..sub.s2, is different in value than uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s2 are used to calculate a second current from the source of the transistor to a drain of the transistor. The uniform resistivity .rho..sub.s1, the uniform resistivity .rho..sub.

Abstract: The present invention provides for a capacitor structure on a semiconductor substrate with an enhanced capacitance. The structure has a first layer of conducting strips parallel to each other on the substrate and a second layer of conducting strips which are parallel to each other. The second layer strips overlie and are substantially congruent to the first layer conducting strips in a top view of the semiconductor substrate. The first layer conducting strips are alternately connected to a first node and a second node, and the second layer conducting strips are alternately connected to the first node and the second node in such a manner that each first layer conducting strip and a second layer conducting strip overlying the first layer conducting strip are connected to different nodes. The first and second nodes form two opposing nodes of the capacitor structure.

Abstract: A process is described for fabricating a self-aligned lateral silicon-controlled rectifier circuit which includes the steps of forming an insulating layer 18 on a semiconductor substrate which includes an upper N-type region 12, 15 and a lower P-type region 10, and then forming an impurity mask 21 on the insulating layer 18. Portions of the insulating layer 18 adjacent the impurity mask 21 are then removed, and P conductivity type impurity 33 is introduced into the substrate 15 except where it is protected by the impurity mask 21. Finally, N-type impurity is introduced, also adjacent the impurity mask 21. When the structure is annealed, the impurity is diffused partially beneath the impurity mask to create a lateral SCR structure having a narrow PNP base width.

Abstract: A vertical bipolar transistor having a subcollector region of two different thicknesses is provided to increase packing density. The thicker portion lies beneath the area between the emitter and the collector contact. A single additional masking step is needed to provide the dual thickness subcollector region.