Abstract: An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises a shift register (SRRD; SRWT) for storing a sequence of bits. The sequence in the shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a clock cycle to the shift register for selected data operations with respect to any of the word storage locations. The selected data operations are a data read or a data write. In response to each clock cycle, received from the circuitry for providing the clock cycle, the shift register shifts the sequence. Further, one bit in the sequence corresponds to an indication of one of the memory word storage locations from which a word will be read or into which a word will be written.

Abstract: A computer program (100, 200) encoded in a computer-programmable medium, and for causing a computer to perform circuit design. The code causes the computer to perform a set of steps. The steps comprise describing a first set of circuitry and describing a second set of circuitry. The steps also comprise describing a digital signal for passing from the first set of circuitry to the second set of circuitry and detecting (230) transitions of the digital signal with respect to a timing constraint (240) of at least a portion of the second set of circuitry. Lastly, the steps comprise, responsive to detecting metastability with respect to timing of a transition of the digital signal relative to the timing constraint of at least a portion of the second set of circuitry, forcing (160) the digital signal to a random value and passing the random value to the second set of circuitry.

Abstract: An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits.

Abstract: An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises a shift register (SRRD; SRWT) for storing a sequence of bits. The sequence in the shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a clock cycle to the shift register for selected data operations with respect to any of the word storage locations. The selected data operations are a data read or a data write. In response to each clock cycle, received from the circuitry for providing the clock cycle, the shift register shifts the sequence. Further, one bit in the sequence corresponds to an indication of one of the memory word storage locations from which a word will be read or into which a word will be written.

Abstract: In one aspect, the present invention provides a method of communicating across a serial line 26. In this method, n parallel streams of data 30 are to be received at a destination 20. In a first embodiment, the n parallel streams of data 30 characterized in that one of streams of data includes a unique characteristic that can be used to distinguish that one from each of the other streams of data. In a second embodiment, each of the n streams of data 30 are in a particular pattern that includes a detectable characteristic. At the destination 20, the unique characteristic and/or detectable characteristic can be detected to correct space and/or time errors in the streams of data. For example, the destination 20 might be a receiver that includes a serial-to-parallel converter 28 and calibration circuitry 34.