Abstract: The present invention discloses a computer implemented method for efficient data movement operations in vector processors comprising a number of logical registers (1), a larger number of physical registers (2), and a set of alias counters (5), wherein each alias counter (5) corresponds to a physical register (2) and stores the number of different logical registers (1) to which said physical register (2) is simultaneously assigned. The method of the invention consists of copying the first v, (vector length (4)) elements of a source vector from a source logical register (8) assigned to a source physical register (10) into a destination vector in a destination logical register (9) assigned to a destination physical register (11).

Abstract: The present invention relates to a method for computing a linear algebra operation of two operands or arrays comprising one or more narrow bit width elements with a digital circuit. The method uses the principle of binary segmentation to reduce the computation overhead of linear algebra operations like linear convolution and inner product of operands such as vectors with narrow bit width components. The invention is also directed to a digital circuit configured to execute the method.

Abstract: Methods and devices for discovering multiple instances of recurring values within a vector are disclosed. A first method calculates the prior instances of the vector. A second method calculates the last unique instances of the vector. An implementation of these methods as SIMD instructions is proposed. Sequential and parallel CAM implementations are also disclosed. The proposed methods can be used to correct conflicting indexes in vector memory indexed operations. Furthermore, an application to a vectorized sorting algorithm is proposed.

Abstract: Methods and devices for discovering multiple instances of recurring values within a vector are disclosed. A first method calculates the prior instances of the vector. A second method calculates the last unique instances of the vector. An implementation of these methods as SIMD instructions is proposed. Sequential and parallel CAM implementations are also disclosed. The proposed methods can be used to correct conflicting indexes in vector memory indexed operations. Furthermore, an application to a vectorized sorting algorithm is proposed.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: The present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operating parameter information, and dynamically estimating a remaining lifetime of the device based on the dynamic usage. Depending on the estimated remaining lifetime, the device may be controlled in a desired manner.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operating parameter information, and dynamically estimating a remaining lifetime of the device based on the dynamic usage. Depending on the estimated remaining lifetime, the device may be controlled in a desired manner. Other embodiments are described and claimed.

Abstract: Methods and apparatus to provide a clustered variations-aware architecture are described. In one embodiment, one or more variations within a clock domain are detected and utilized to adjust a clock signal of the clock domain.

Abstract: Embodiments of apparatuses and methods for reducing the soft error vulnerability of stored data are disclosed. In one embodiment, an apparatus includes storage logic, determination logic, and selection logic. The determination logic is to determine a condition of a dataword. The storage logic includes logic to store a first portion of the dataword, a second portion of the dataword, and a result generated by the determination logic. The selection logic is to select, based on the contents of the storage logic to store the result, either the contents of the storage logic to store the second portion of the dataword, or a replacement value. The replacement value depends on the contents of a predetermined bit of the storage logic to store the first portion of the dataword.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed.

Abstract: An NBTI-resilient memory cell is made up of a ring of multiple NAND gates. The NAND gates are arranged such that one of the NAND gates has a “0” in its output, while the remaining NAND gates have a “1” in their outputs. PMOS transistors within the memory cell experience less degradation than in inverter-based memory cells. Guard-banding to account for transistor degradation may be mitigated, or the operating frequency of the memory cell may be increased.

Abstract: An NBTI-resilient memory cell is made up of a ring of multiple NAND gates. The NAND gates are arranged such that one of the NAND gates has a “0” in its output, while the remaining NAND gates have a “1” in their outputs. PMOS transistors within the memory cell experience less degradation than in inverter-based memory cells. Guard-banding to account for transistor degradation may be mitigated, or the operating frequency of the memory cell may be increased.

Abstract: Methods and apparatus to provide a clustered variations-aware architecture are described. In one embodiment, one or more variations within a clock domain are detected and utilized to adjust a clock signal of the clock domain.

Abstract: Embodiments of apparatuses and methods for reducing the soft error vulnerability of stored data are disclosed. In one embodiment, an apparatus includes storage logic, determination logic, and selection logic. The determination logic is to determine a condition of a dataword. The storage logic includes logic to store a first portion of the dataword, a second portion of the dataword, and a result generated by the determination logic. The selection logic is to select, based on the contents of the storage logic to store the result, either the contents of the storage logic to store the second portion of the dataword, or a replacement value. The replacement value depends on the contents of a predetermined bit of the storage logic to store the first portion of the dataword.

Abstract: A processor including a pipeline for processing a plurality of instructions is disclosed. The pipeline comprises a plurality of stages. Each stage comprises a processing logic, and a control logic. The processing logic processes an input to produce an output. The control logic receives the output of the processing logic, and provides an intermediate and final output of the processing logic. The intermediate output is provided at a fraction of one cycle of a clock signal after receiving the input. The final output is produced at one cycle of a clock signal after receiving the input. The control logic also detects errors, and stalls the pipeline for one cycle of the clock signal when an error is detected.