Patents by Inventor OSNAT ARAD

OSNAT ARAD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium
    Patent number: 9235673
    Abstract: An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. Optionally, the apparatus comprises a timing improver. The apparatus selects a candidate output pin of an IP block that is a node on at least two timing paths that have contradictory timing violations. The candidate output pin is cloned and at least one of the timings paths is connected to the cloned output pin for one of the instances of the IP block.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 12, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Amir Grinshpon, Osnat Arad, Asher Berkovitz
  • APPARATUS FOR AND A METHOD OF MAKING A HIERARCHICAL INTEGRATED CIRCUIT DESIGN OF AN INTEGRATED CIRCUIT DESIGN, A COMPUTER PROGRAM PRODUCT AND A NON-TRANSITORY TANGIBLE COMPUTER READABLE STORAGE MEDIUM
    Publication number: 20150347655
    Abstract: An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. Optionally, the apparatus comprises a timing improver. The apparatus selects a candidate output pin of an IP block that is a node on at least two timing paths that have contradictory timing violations. The candidate output pin is cloned and at least one of the timings paths is connected to the cloned output pin for one of the instances of the IP block.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: AMIR GRINSHPON, OSNAT ARAD, ASHER BERKOVITZ