Abstract: A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and writes data to the memory cell(s) and may perform other functions necessary for facilitating the data read, write and hold. The randomization circuitry randomizes operations performed by the peripheral circuitry to reduce a correlation between the data and the current consumed by the hardware memory.

Abstract: A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.

Abstract: A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.

Abstract: A logic element includes a logic block, a supply voltage input, switchable power gates and a gate selector. The logic block implements a logic function on input data to obtain at least one output data signal. The switchable power gates transfer a supply voltage from the supply voltage input to the logic block in accordance with respective gate control signals. At least two of the power gates have different respective electrical properties. The gate selector switches on differing ones of the power gates in accordance with gate selection data.

Abstract: A randomization element includes a logic input for inputting a logic signal, a logic output for outputting the input logic signal at a delay and a randomization element. The randomization elements introduces the delay between said logic input and said logic output and operates selectably in static mode and in dynamic mode in accordance with a mode control signal. A logic circuit may be formed with randomization elements interspersed amongst the logic gates, to obtain protection against side channel attacks by inputting a selected control sequence into the randomization elements.

Abstract: A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and writes data to the memory cell(s) and may perform other functions necessary for facilitating the data read, write and hold. The randomization circuitry randomizes operations performed by the peripheral circuitry to reduce a correlation between the data and the current consumed by the hardware memory.

Abstract: A logic element includes a logic block, a supply voltage input, switchable power gates and a gate selector. The logic block implements a logic function on input data to obtain at least one output data signal. The switchable power gates transfer a supply voltage from the supply voltage input to the logic block in accordance with respective gate control signals. At least two of the power gates have different respective electrical properties. The gate selector switches on differing ones of the power gates in accordance with gate selection data.

Abstract: A logic element includes a logic block, a clock generator, a clock assigner and at least one sampling element. The logic block implements a logic function on input data to obtain a plurality output data signals. The output data signals are sampled by respective clock signals. The clock generator generates phase-shifted clock signals from a reference clock signal. The clock assigner assigns differing ones of the phase-shifted clock signals to respective output data signals. The sampling element(s) sample the output data signals in accordance with the respective assigned phase-shifted clock signals.

Abstract: A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes: obtaining an initial circuit design; specifying respective delays for multiple logic paths in the initial circuit design such that at least some of the outputs switch at different times within a clock cycle for different combinations of logic input levels; and forming a second circuit design having the specified respective delays along the respective logic paths by adding delay elements to the initial circuit design based on the specified respective delays.

Abstract: A method for detecting errors is performed on a data string which includes an information portion and a redundancy portion. The information portion includes two or more sub-strings. The method includes generating respective redundancy words for each sub-string by encoding each sub-string with a separable robust code. A composite redundancy word is generated from respective redundancy words. An error is flagged when the redundancy portion of said data string differs from the composite redundancy word.

Abstract: A logic element includes a logic block, a clock generator, a clock assigner and at least one sampling element. The logic block implements a logic function on input data to obtain a plurality output data signals. The output data signals are sampled by respective clock signals. The clock generator generates phase-shifted clock signals from a reference clock signal. The clock assigner assigns differing ones of the phase-shifted clock signals to respective output data signals. The sampling element(s) sample the output data signals in accordance with the respective assigned phase-shifted clock signals.

Abstract: A bit generator includes a sampler and a voltage controlled oscillator (VCO) powered by a supply voltage. The sampler outputs a non-deterministic bit series which is generated by sampling an output of the VCO. The randomness of the non-deterministic bit series depends on inherent background noise and/or inherent clock jitter. Optionally, the bit generator does not include noise source circuitry.

Abstract: A randomization element includes a logic input for inputting a logic signal, a logic output for outputting the input logic signal at a delay and a randomization element. The randomization elements introduces the delay between said logic input and said logic output and operates selectably in static mode and in dynamic mode in accordance with a mode control signal. A logic circuit may be formed with randomization elements interspersed amongst the logic gates, to obtain protection against side channel attacks by inputting a selected control sequence into the randomization elements.

Abstract: An RMTL gate includes at least two logic blocks, where at least one of the logic blocks operates in multiple modes. The respective logic block mode(s) are selected by a topology selector which applies mode control signals to the logic blocks in order to obtain a selected topology for logic circuit operation. RMTL logic gates may be cascaded and/or interconnected to form an RMTL logic circuit with multiple logic gates which may operate with dynamically varying topologies. Use of random, semi-random or specified control sequences may protect the logic circuit against security attacks.

Abstract: A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes: obtaining an initial circuit design; specifying respective delays for multiple logic paths in the initial circuit design such that at least some of the outputs switch at different times within a clock cycle for different combinations of logic input levels; and forming a second circuit design having the specified respective delays along the respective logic paths by adding delay elements to the initial circuit design based on the specified respective delays.

Abstract: An RMTL gate includes at least two logic blocks, where at least one of the logic blocks operates in multiple modes. The respective logic block mode(s) are selected by a topology selector which applies mode control signals to the logic blocks in order to obtain a selected topology for logic circuit operation. RMTL logic gates may be cascaded and/or interconnected to form an RMTL logic circuit with multiple logic gates which may operate with dynamically varying topologies. Use of random, semi-random or specified control sequences may protect the logic circuit against security attacks.

Abstract: An apparatus includes a plurality of AND gates each to receive as input a bit of a first binary vector and a corresponding bit of a second binary vector, where the length of the first binary vector is not greater than the length of the second binary vector. The apparatus also includes a multiple input XOR gate to calculate in a single cycle a scalar product of the first binary vector and the second binary vector by performing an exclusive OR operation on the output of each of the AND gates.