Patents by Inventor Osvaldo Colavin
Osvaldo Colavin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140176587Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: ApplicationFiled: March 3, 2014Publication date: June 26, 2014Applicant: STMicroelectronics, IncInventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Patent number: 8681164Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: GrantFiled: October 18, 2012Date of Patent: March 25, 2014Assignee: STMicroelectronics, Inc.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Patent number: 8667252Abstract: Clustered VLIW processing elements, each preferably simple and identical, are coupled by a runtime reconfigurable inter-cluster interconnect to form a coprocessor executing only those portions of a program having high instruction level parallelism. The initial portion of each program segment executed by the coprocessor reconfigures the interconnect, if necessary, or is skipped. Clusters may be directly connected to a subset of neighboring clusters, or indirectly connected to any other cluster, a hierarchy exposed to the programming model and enabling a larger number of clusters to be employed. The coprocessor is idled during remaining portions of the program to reduce power dissipation.Type: GrantFiled: November 21, 2002Date of Patent: March 4, 2014Assignee: STMicroelectronics, Inc.Inventors: Osvaldo Colavin, Davide Rizzo
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Patent number: 8314808Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: GrantFiled: September 21, 2011Date of Patent: November 20, 2012Assignee: STMicroelectronics, Inc.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Patent number: 8166321Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.Type: GrantFiled: April 28, 2008Date of Patent: April 24, 2012Assignee: STMicroelectronics, Inc.Inventors: Davide Rizzo, Osvaldo Colavin
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Patent number: 8099585Abstract: Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source operand is true. The predicate bit, if any, of the destination register is set to the logical AND of the source registers' predicates. Similarly, in a non-programmable processor synthesized with predicated operand support, an operator will perform the associated function depending on the state of inputs' predicates. The output predicate is evaluated as the logical AND of the inputs' predicates. An additional bit for each data register, a change in the semantics of the instructions to include predication, and a few additional instructions to save and restore register predicate bits and to specifically set or reset a register's predicate bit are required.Type: GrantFiled: August 9, 2007Date of Patent: January 17, 2012Assignee: STMicroelectronics, Inc.Inventors: Osvaldo Colavin, Davide Rizzo
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Publication number: 20120007871Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: ApplicationFiled: September 21, 2011Publication date: January 12, 2012Applicant: STMicroelectronics, Inc.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Patent number: 8054315Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: GrantFiled: January 27, 2011Date of Patent: November 8, 2011Assignee: STMicroelectronics, Inc.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Publication number: 20110122946Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: ApplicationFiled: January 27, 2011Publication date: May 26, 2011Applicant: STMICROELECTRONICS, INC.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Patent number: 7898548Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: GrantFiled: August 16, 2010Date of Patent: March 1, 2011Assignee: STMicroelectronics, Inc.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Publication number: 20100309211Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: ApplicationFiled: August 16, 2010Publication date: December 9, 2010Applicant: STMICROELECTRONICS, INC.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Patent number: 7836279Abstract: A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable to receive a shift mask signal and a shift signal and to identify a shifting register queue within the register file based on the shift mask signal. The shifting register queue comprises a plurality of queue registers. The register file is further operable to shift the contents of the queue registers based on the shift signal.Type: GrantFiled: December 31, 2003Date of Patent: November 16, 2010Assignee: STMicroelectronics, Inc.Inventors: Osvaldo Colavin, Vineet Soni, Davide Rizzo
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Patent number: 7777753Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: GrantFiled: April 15, 2009Date of Patent: August 17, 2010Assignee: STMicroelectronics, Inc.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Patent number: 7707216Abstract: A data sorter includes a storage sorter that sorts a data set according to a defined criteria; and a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to a key value. The storage sorter includes a priority queue for sorting the data set. The priority queue has M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism includes a plurality of comparison circuits, each of which is capable of detecting whether one of the intermediate sorted data values is equal to the key value or, if no match exists, extracting a minimal value greater than (or less than according to a defined criteria) the key value.Type: GrantFiled: October 8, 2002Date of Patent: April 27, 2010Assignee: STMicroelectronics, Inc.Inventors: Davide Rizzo, Osvaldo Colavin
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Publication number: 20090313458Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.Type: ApplicationFiled: August 20, 2009Publication date: December 17, 2009Applicant: STMicroelectronics Inc.Inventors: Osvaldo Colavin, Davide Rizzo, Vineet Soni
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Patent number: 7594102Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.Type: GrantFiled: December 15, 2004Date of Patent: September 22, 2009Assignee: STMicroelectronics, Inc.Inventors: Osvaldo Colavin, Davide Rizzo, Vineet Soni
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Publication number: 20090201305Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: ApplicationFiled: April 15, 2009Publication date: August 13, 2009Applicant: STMICROELECTRONICS, INC.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Patent number: 7542045Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.Type: GrantFiled: December 13, 2007Date of Patent: June 2, 2009Assignee: STMicroelectronics, Inc.Inventors: Jefferson Eugene Owen, Raul Zegers Diaz, Osvaldo Colavin
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Publication number: 20080201590Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.Type: ApplicationFiled: April 28, 2008Publication date: August 21, 2008Applicant: STMICROELECTRONICS, INC.Inventors: Davide Rizzo, Osvaldo Colavin
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Patent number: 7366932Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.Type: GrantFiled: October 30, 2002Date of Patent: April 29, 2008Assignee: STMicroelectronics, Inc.Inventors: Davide Rizzo, Osvaldo Colavin