Patents by Inventor Oswald Becca
Oswald Becca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8533522Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: September 21, 2012Date of Patent: September 10, 2013Assignee: MOSAID Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 8296598Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: May 23, 2011Date of Patent: October 23, 2012Assignee: Mosaid Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 8209562Abstract: In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow.Type: GrantFiled: January 7, 2010Date of Patent: June 26, 2012Assignee: Mosaid Technologies IncorporatedInventors: Jody Defazio, Oswald Becca, Peter Nyasulu
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Patent number: 8069363Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: August 19, 2009Date of Patent: November 29, 2011Assignee: Mosaid Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Publication number: 20110228626Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: ApplicationFiled: May 23, 2011Publication date: September 22, 2011Inventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Publication number: 20100122104Abstract: In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow.Type: ApplicationFiled: January 7, 2010Publication date: May 13, 2010Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Jody DEFAZIO, Oswald BECCA, Peter NYASULU
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Publication number: 20100033216Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: ApplicationFiled: August 19, 2009Publication date: February 11, 2010Applicant: MOSAID Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 7661010Abstract: A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.Type: GrantFiled: September 29, 2006Date of Patent: February 9, 2010Assignee: Mosaid Technologies IncorporatedInventors: Jody DeFazio, Oswald Becca, Peter Nyasulu
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Patent number: 7596710Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: December 14, 2005Date of Patent: September 29, 2009Assignee: MOSAID Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 7558909Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.Type: GrantFiled: October 12, 2006Date of Patent: July 7, 2009Assignee: Satech Group A.B. Limited Liability CompanyInventors: Alan Roth, Robert McKenzie, Oswald Becca
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Patent number: 7478193Abstract: A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.Type: GrantFiled: May 19, 2006Date of Patent: January 13, 2009Assignee: MOSAID Technologies IncorporatedInventors: Oswald Becca, Alan Roth, Robert McKenzie
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Publication number: 20080045338Abstract: A system for allowing a user to remotely access a game includes: a game console; a remote console client configured to receive a game control signal; and a remote console server. The remote console server includes an audio and video encoder configured to receive an audio output and a video output from the game console and to convert the audio output and the video output to a network packet. The remote console server also includes: a game controller emulation unit and a network interface configured to send and receive the network packet. The game controller emulation unit is configured to receive a game controller signal from the game console and to send the game controller signal to the remote console client and to receive a game controller input from the remote console client and send the game controller input to the game console.Type: ApplicationFiled: June 11, 2007Publication date: February 21, 2008Inventors: Peter Walker, Oswald Becca
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Publication number: 20070283182Abstract: A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.Type: ApplicationFiled: September 29, 2006Publication date: December 6, 2007Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Jody DEFAZIO, Oswald BECCA, Peter NYASULU
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Publication number: 20070133244Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.Type: ApplicationFiled: October 12, 2006Publication date: June 14, 2007Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Alan ROTH, Robert MCKENZIE, Oswald BECCA
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Publication number: 20070008759Abstract: A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.Type: ApplicationFiled: May 19, 2006Publication date: January 11, 2007Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Oswald Becca, Alan Roth, Robert McKenzie
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Patent number: 7136961Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.Type: GrantFiled: January 31, 2003Date of Patent: November 14, 2006Assignee: Mosaid Technologies, Inc.Inventors: Alan Roth, Robert McKenzie, Oswald Becca
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Patent number: 7062601Abstract: A cam system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMS in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for co-ordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimising the number of CAMs being connected to a common forwarding bus.Type: GrantFiled: May 7, 2003Date of Patent: June 13, 2006Assignee: Mosaid Technologies IncorporatedInventors: Oswald Becca, Alan Roth, Robert McKenzie
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Publication number: 20060103439Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: ApplicationFiled: December 14, 2005Publication date: May 18, 2006Inventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 7010713Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: January 27, 2003Date of Patent: March 7, 2006Assignee: MOSAID Technologies, Inc.Inventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Publication number: 20040123175Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: ApplicationFiled: January 27, 2003Publication date: June 24, 2004Applicant: MOSAID Technologies, Inc.Inventors: Alan Roth, Oswald Becca, Pedro Ovalle