Abstract: The invention relates to a shifter stage for a variable-length digital code decoder which decodes one code per clock cycle, reads input data arriving from a memory, supplies a logical unit on each cycle with a word having the size of the longest variable-length code to be decoded, receives from the logical unit the number of bits of the code decoded on the preceding clock cycle, and effects a shift in the data read equal to the cumulative total of the lengths of codes decoded since the last read of input data.It comprises a first barrel shift register (11) which reads the input data and performs a shift in the data read equal to the cumulative total of the lengths of the codes decoded between the preceding cycle and the start of the last read, and a second barrel shift register (13) which receives the data arriving from the first register and performs a shift equal to the length of the code decoded on the preceding cycle.

Abstract: The invention relates to a digital processing circuit comprising a host interface (7) which provides access from the processing circuit's bus (6) to an external data processing system (8). The processing circuit is broken down into blocks (1, 2, 3) with test registers (4, 5) interposed between an upstream block and a downstream block. The test registers (4, 5) are connected to the bus (6) and identified by an address allowing data to be sent to them or read from them.