Abstract: A method is provided for improving silicide formation, and the electrical ntact provided thereby, on non-planar silicon structures. In this method, a semiconductor device structure is initially formed having non-planar surface regions. A metal layer is deposited on the non-planar surfaces. The metal deposition process step is followed by an off-axis implantation of non-dopant ions, causing a mixing of the metal and silicon atoms at the metal and non-planar silicon structure interface. The off-axes implantation also serves to disrupt the native silicon dioxide layer between the silicon and metal layers regions. Thermal processing is then used to form silicide on the non-planar surfaces of the semiconductor silicon structure.

Abstract: A method for fabricating complementary enhancement and depletion mode field ffect transistors on a single substrate comprises the steps of: a) patterning a structure of a layer of silicon formed on an insulating substrate to form first, second, third, and fourth silicon islands; b) doping the second island with a p-type dopant; c) doping the third island with a p-type dopant; d) doping the fourth island with an n-type dopant; e) forming a first electrically insulating gate layer on the third and fourth islands; f) forming a second electrically insulating gate on the first and second islands; g) forming an electrically conductive gate over the first and second electrically insulating gate layers; h) doping the second island with an n-type dopant; i) doping the fourth island with an n-type dopant; j) doping the first and third islands with a p-type dopant; and k) doping the first and third islands with a p-type dopant to transform the first island into a p-type enhancement mode field effect transistor, the seco