Abstract: A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

Abstract: A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A method and device are provided for retrieving system data needed for boot up and/or wake-up. A bus hub is provided that retrieves needed data prior to such data being requested by the processor. The bus hub then stores the data. When a request is received for the data from the processor, the bus hub responds by sending the stored data.

Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

Abstract: A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: Techniques are disclosed relating to resource contention resolution in a pre-memory environment. Prior to system memory being accessible, a resource control processing element controls access to a hardware resource by a plurality of processing elements by granting received requests from the processing elements for access to the resource. The resource control processing element may prioritize requests based on a determined amount of utilization of the hardware resource by individual ones of the processing elements. In one embodiment, processing elements request for information from a bus controller (e.g., an SMBus controller) that is usable to initialize system memory. The resource control processing element may respond to the requests by retrieving the requested information from the controller and providing that information to the processing element or by retrieving the requested information from a cache and providing that information to the processing element.

Abstract: Techniques and structures are disclosed in which memory training for DDR or other memory can be performed more rapidly. A memory controller is configured so that one or more memory parameters (e.g., timing delay) can be determined for one or more hardware elements such as delay locked loops (DLLs). Training may be performed without intermediation by (or reporting of results to) a system BIOS. Thus, training may be performed fully in hardware. Voltage training techniques are also disclosed.

Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

Abstract: During a boot process of a data processing device having a master bootstrap processor device and multiple slave processor devices, memory associated with the master bootstrap processor is not accessible. Accordingly, the master bootstrap processor communicates configuration information to a slave processor by writing configuration information to a register associated with the slave processor. The slave processor communicates an acknowledgment to the master bootstrap processor in response to reading the configuration information.

Abstract: A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event indicator, a third link is established between the first processor device and the second memory module at a third time, the third time after the first time and the second time.

Abstract: Techniques are disclosed relating to resource contention resolution in a pre-memory environment. Prior to system memory being accessible, a resource control processing element controls access to a hardware resource by a plurality of processing elements by granting received requests from the processing elements for access to the resource. The resource control processing element may prioritize requests based on a determined amount of utilization of the hardware resource by individual ones of the processing elements. In one embodiment, processing elements request for information from a bus controller (e.g., an SMBus controller) that is usable to initialize system memory. The resource control processing element may respond to the requests by retrieving the requested information from the controller and providing that information to the processing element or by retrieving the requested information from a cache and providing that information to the processing element.

Abstract: In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.

Abstract: A memory subsystem configured to perform event-driven training. The memory subsystem includes a memory, a memory controller coupled to the memory, and a monitoring unit coupled to the memory controller. The monitoring unit is configured to monitor at least one parameter of the memory subsystem, determine whether at least one parameter is within a specified range, and provide an indication to the memory controller if at least one parameter is not within the specified range. The memory controller is configured to perform a training procedure responsive to receiving the indication. Performing the training procedure includes the memory controller performing at least one write to memory, at least one read from memory, and adjusting a delay for one or more signals conveyed between the memory controller and the memory.