Abstract: Systems, apparatuses, and methods for performing secure system memory training are disclosed. In one embodiment, a system includes a boot media, a security processor with a first memory, a system memory, and one or more main processors coupled to the system memory. The security processor is configured to retrieve first data from the boot media and store and authenticate the first data in the first memory. The first data includes a first set of instructions which are executable to retrieve, from the boot media, a configuration block with system memory training parameters. The security processor also executes a second set of instructions to initialize and train the system memory using the training parameters. After training the system memory, the security processor retrieves, authenticates, and stores boot code in the system memory and releases the one or more main processors from reset to execute the boot code.

Abstract: Systems, apparatuses, and methods for performing secure system memory training are disclosed. In one embodiment, a system includes a boot media, a security processor with a first memory, a system memory, and one or more main processors coupled to the system memory. The security processor is configured to retrieve first data from the boot media and store and authenticate the first data in the first memory. The first data includes a first set of instructions which are executable to retrieve, from the boot media, a configuration block with system memory training parameters. The security processor also executes a second set of instructions to initialize and train the system memory using the training parameters. After training the system memory, the security processor retrieves, authenticates, and stores boot code in the system memory and releases the one or more main processors from reset to execute the boot code.

Abstract: A method of booting a multi-processor data processing device includes establishing a link between a first processor and a memory. The link is monitored to determine if, in response to a request from the processor, expected initialization data is communicated between the memory and the first processor. If unexpected data is detected on the link, the link is severed and a new link established between a second processor and the memory to allow the second processor to initiate the boot process. This ensures that, in the event of an error in the boot process at the first processor, the device can complete the boot process, thereby reducing device downtime.

Abstract: Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).

Abstract: Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).

Abstract: A method of booting a multi-processor data processing device includes establishing a link between a first processor and a memory. The link is monitored to determine if, in response to a request from the processor, expected initialization data is communicated between the memory and the first processor. If unexpected data is detected on the link, the link is severed and a new link established between a second processor and the memory to allow the second processor to initiate the boot process. This ensures that, in the event of an error in the boot process at the first processor, the device can complete the boot process, thereby reducing device downtime.

Abstract: Disclosed herein are techniques and methods for identifying a target onboard memory buffer device from a system address of a computer system. The techniques and methods can be employed in a computer system having a system controller, main memory having memory devices, and onboard memory buffer devices between the system controller and the main memory. One embodiment of the method obtains a system address that conveys a physical address within the computer system, decodes the system address to determine a target channel controller in the computer system, and identifies at least one memory buffer device associated with the target channel controller.

Abstract: Methods and apparatus are provided for use in testing a memory (220, 230, 240) in a multiprocessor computer system (200). The multiprocessor computer system (200) has a plurality of processing nodes (210-217) coupled in an array wherein each processing node is coupled to at least one other processing node, and a memory (220, 230, 240) distributed among the plurality of processing nodes (210-217). A configuration of the array is determined. An initial configuration of the memory (220, 230, 240) is also determined. The memory (220, 230, 240) is tested over the array according to the initial configuration to identify a bad memory element. The initial configuration is modified to form a revised configuration that excludes the bad memory element.