Abstract: A memory system uses standard memory devices not normally supporting parity bits. Parity bits for multiple memory devices are stored in a dedicated parity device shared among multiple memory devices. Inadvertent erasure of the parity information, when writing to a single memory device, is prevented by a prereading of the parity device prior to a writing to the single memory device. Special circuitry stores the preread parity information and merges it back with the calculated parity bit for the written data to preserve complete parity information.

Abstract: A programmable controller has a rack that electrically connects a number of I/O modules to a processor module. The processor module includes a external device communication interface section and a general purpose processor section electrically coupled together by a set of common buses. Both of these module sections include a microprocessor and memory connected by an internal set of buses which are isolatable from the set of common buses. The isolation capability permits the different sections to perform their operations simultaneously. A shared system memory and an rack interface are coupled to the common buses for the exchange of data with the I/O modules. A unique ladder logic processor also is connected directly to the common buses. The ladder logic processor includes a hardwired Boolean bit logic processor and a custom microcoded processor to execute instructions of a ladder type control program.

Abstract: A programmable controller has a rack that electrically connects a number of I/O modules to a processor module. The processor module includes a external device communication interface section and a general purpose processor section electrically coupled together by a set of common buses. Both of these module sections include a microprocessor and memory connected by an internal set of buses which are isolatable from the set of common buses. The isolation capability permits the different sections to perform their operations simultaneously. A shared system memory and an rack interface are coupled to the common buses for the exchange of data with the I/O modules. A unique ladder logic processor also is connected directly to the common buses. The ladder logic processor includes a hardwired Boolean bit logic processor and a custom microcoded processor to execute instructions of a ladder type control program.