Abstract: An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.

Abstract: A circuit card of an industrial controller may be removed or inserted under power without loss of memory or disturbance to the power supplies of other modules through the use of a power failure signal derived from shortened pins on the connector between the card and the industrial controller. The power failure signal activates a timer delaying connection of the board components to power until the physical connection between the card and the industrial controller has stabilized. At this time current drain is ramped up by a controlling series FET. Upon removal of the card, the power failure signal causes outputs of an on-board microprocessor to be pulled to particular states necessary to prevent disturbance of a battery backed-up RAM and to eliminate current flow through protection diodes on other memory type devices attached to the microprocessor.

Abstract: A method of editing a real-time control program as it controls equipment is provided in which the editing occurs in a second area of memory and integrated into the pre-existing program by means of conditional jump instructions concatenated to that edited material. The pre-existing program is uninterrupted by the editing process except for a change of single instructions which do not affect the results of the execution but redirect the execution thread of that control program to be conditionally connected to the edited material. This single writing of single instructions, which do not affect execution results, precludes the possibility of the controller executing partially edited programs. The jump instructions are conditional on a test edit pointer to allow instantaneous implementation of the edits and a simple return to unedited instructions simply by changing the state of the flag.

Abstract: A co-processor interface allows both a general processor and a relay ladder processor to make repeated calls to each other in the execution of subroutines. A register transfer instruction detected by the relay ladder processor triggers a suspension of the general processor. Return of control to the general processor is accomplished at the same time a register value is provided to the general processor that the general processor uses to reinitialize its program counter. For most single level transfers of control, a single transition instruction between the general processor to the relay ladder processor is sufficient to perform a call.

Abstract: A multi-tasking industrial controller for real-time control of machinery and the like permits the use of both periodic and event driven tasks by establishing a hierarchy of both task types in the form of priorities that resolve conflicts between events of the same and different types. Each task may access a common "global" memory area to communicate information and timing with other tasks and so as to coordinate the overall industrial control process. Trouble-shooting of the task software is made possible by a hardware address monitor which may be programmed to identify access of a particular memory location or range by any task and to record information about the particular task causing that global memory access.

Abstract: A programmable controller includes a main processor which executes a user control program. The main processor is interrupted by a support processor which operates as a real time clock. The interval between interrupts is determined by instructions within the user control program and may be dynamically altered when required. The main processor executes a user created interrupt routine when each interrupt occurs.

Abstract: An eight-bit microprocessor sequentially reads controller type instructions from a memory and applies the operation codes of selected ones of the instructions to a hardwired Boolean processor. The microprocessor also couples status words between an I/O image table stored in the memory and the I/O interface racks which connect the programmable controller to the machine being controlled. In general, those controller type instructions which are word oriented are executed by the microprocessor and those which are single-bit oriented are executed by the Boolean processor. The Boolean processor is operable in combination with the microprocessor to examine selected status bits in the I/O image table and to set selected status bits therein to a logic state which is determined in part by the state of the examined status bits.