Patents by Inventor Otto Andreas Torreiter
Otto Andreas Torreiter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240019488Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.Type: ApplicationFiled: September 29, 2023Publication date: January 18, 2024Inventors: Thomas Gentner, Alejandro Alberto Cook Lobo, Otto Andreas Torreiter
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Patent number: 11808808Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.Type: GrantFiled: December 8, 2021Date of Patent: November 7, 2023Assignee: International Business Machines CorporationInventors: Thomas Gentner, Alejandro Alberto Cook Lobo, Otto Andreas Torreiter
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Publication number: 20230176116Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system.Type: ApplicationFiled: December 8, 2021Publication date: June 8, 2023Inventors: Thomas Gentner, Alejandro Alberto Cook Lobo, Otto Andreas Torreiter
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Patent number: 11574695Abstract: A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.Type: GrantFiled: July 29, 2021Date of Patent: February 7, 2023Assignee: International Business Machines CorporationInventors: Alejandro Alberto Cook Lobo, Thomas Gentner, Michael B. Kugel, Otto Andreas Torreiter
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Publication number: 20230035157Abstract: A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Inventors: Alejandro Alberto Cook Lobo, Thomas Gentner, Michael B. Kugel, Otto Andreas Torreiter
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Patent number: 11262381Abstract: The invention relates to a device for positioning a semiconductor die in a wafer prober, the device comprising a carrier plate and a clamp on a front surface of the carrier plate, the dimensions of the carrier plate matching a standard geometry required by the wafer prober for receiving a semiconductor wafer to be probed by the wafer prober, the clamp being reversibly movable against a force of an elastic element between an open position and a closed position, the clamp being adapted for fixing the die on the carrier plate in the closed position and for releasing the die in the open position.Type: GrantFiled: January 10, 2020Date of Patent: March 1, 2022Assignee: International Business Machines CorporationInventors: Otto Andreas Torreiter, Jörg Georg Appinger, Martin Eckert, Quintino Lorenzo Trianni
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Patent number: 11239152Abstract: The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.Type: GrantFiled: September 4, 2019Date of Patent: February 1, 2022Assignee: International Business Machines CorporationInventors: Otto Andreas Torreiter, Thomas Gentner, Martin Eckert
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Patent number: 11209479Abstract: Various aspects of the present invention disclose a test device that includes a retaining element retaining one or more nuclear radiation sources for performing a nuclear radiation stress test of data storage structures of integrated circuits on a wafer in a wafer prober. The retaining element includes one or more apertures for applying nuclear radiation from the one or more nuclear radiation sources to the data storage structures. The retaining element is configured for controlling the nuclear radiation applied via the one or more apertures. The controlling includes a varying of relative positions of the one or more nuclear radiation sources and the one or more apertures. Additional aspects of the present invention disclose a testing method, computer program product, and computer system for performing the nuclear radiation stress test. In an example aspect, embodiments of the present invention disclose a test device for a wafer prober.Type: GrantFiled: October 29, 2019Date of Patent: December 28, 2021Assignee: International Business Machines CorporationInventors: Martin Eckert, Matthias Pflanz, Otto Andreas Torreiter, Juergen Pille
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Publication number: 20210215738Abstract: The invention relates to a device for positioning a semiconductor die in a wafer prober, the device comprising a carrier plate and a clamp on a front surface of the carrier plate, the dimensions of the carrier plate matching a standard geometry required by the wafer prober for receiving a semiconductor wafer to be probed by the wafer prober, the clamp being reversibly movable against a force of an elastic element between an open position and a closed position, the clamp being adapted for fixing the die on the carrier plate in the closed position and for releasing the die in the open position.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Inventors: Otto Andreas Torreiter, Jörg Georg Appinger, Martin Eckert, Quintino Lorenzo Trianni
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Publication number: 20210123969Abstract: Various aspects of the present invention disclose a test device that includes a retaining element retaining one or more nuclear radiation sources for performing a nuclear radiation stress test of data storage structures of integrated circuits on a wafer in a wafer prober. The retaining element includes one or more apertures for applying nuclear radiation from the one or more nuclear radiation sources to the data storage structures. The retaining element is configured for controlling the nuclear radiation applied via the one or more apertures. The controlling includes a varying of relative positions of the one or more nuclear radiation sources and the one or more apertures. Additional aspects of the present invention disclose a testing method, computer program product, and computer system for performing the nuclear radiation stress test. In an example aspect, embodiments of the present invention disclose a test device for a wafer prober.Type: ApplicationFiled: October 29, 2019Publication date: April 29, 2021Inventors: Martin Eckert, Matthias Pflanz, Otto Andreas Torreiter, Juergen Pille
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Publication number: 20210066183Abstract: The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.Type: ApplicationFiled: September 4, 2019Publication date: March 4, 2021Inventors: Otto Andreas Torreiter, Thomas Gentner, Martin Eckert
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Patent number: 7650554Abstract: A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.Type: GrantFiled: November 28, 2006Date of Patent: January 19, 2010Assignee: International Business Machines CorporationInventors: Gottfried Goldrian, Otto Andreas Torreiter, Dieter Wendel
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Patent number: 6774656Abstract: The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.Type: GrantFiled: November 1, 2001Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Ulrich Baur, Otto Andreas Torreiter, Joseph Eckelman, David TinSun Hui
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Patent number: 6725171Abstract: The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type (50, 52) and N-type (54, 56), respectively, are split into at least two sub-devices P1, P2 and N1, N2, and are controlled separately by a control logic (60, 62, 64, 70, 72, 74). Then, for example N2 is used for testing the P device, and P2 is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.Type: GrantFiled: November 1, 2001Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: Ulrich Baur, Otto Andreas Torreiter, Joseph Eckelman, David TinSun Hui
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Publication number: 20020079915Abstract: The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.Type: ApplicationFiled: November 1, 2001Publication date: June 27, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ulrich Baur, Otto Andreas Torreiter, Joseph Eckelman, David TinSun Hui
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Publication number: 20020078400Abstract: The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type(50, 52) and N-type(54,56), respectively, are split into at least two sub-devices P1, P2 and N1, N2, and are controlled separately by a control logic (60,62,64,70,72,74). Then, for example N2 is used for testing the P device, and P2 is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.Type: ApplicationFiled: November 1, 2001Publication date: June 20, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ulrich Baur, Otto Andreas Torreiter, Joseph Eckelman, David TinSun Hui
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Publication number: 20020043984Abstract: An apparatus for temporarily attaching an integrated circuit chip to a chip carrier for subsequent electrical testing of the integrated circuit chip is provided consisting of a support carrier and a compression adjusting device to apply a compressive force via the support carrier to the integrated circuit chip to be tested, whereby the support carrier is arranged between the compression adjusting device and the integrated circuit chip to be tested, as well as a method for temporarily attaching an integrated circuit chip to a chip carrier. Furthermore, the support carrier is adapted to function as a transport vehicle for the integrated circuit chip.Type: ApplicationFiled: October 10, 2001Publication date: April 18, 2002Applicant: International Business Machines CorporationInventor: Otto Andreas Torreiter