Abstract: A serial-parallel-serial organized charge transfer memory is integrated on a semiconductor chip and includes a read-in chain consisting of first and second charge transfer elements alternately arranged behind one another, respectively controllable by way of clock pulse lines, and comprising memory and shift electrodes, and a field of parallel chains of charge transfer elements into which charges characterizing information are transferred either only from the first or only from the second charge transfer elements of the read-in chain, and a read-out chain constructed as the read-in chain and operated by way of clock pulse lines. The like electrodes of the charge transfer elements of the read-in and read-out chains, together with the appertaining control and clock pulse lines respectively consist of a continuous conduction band, at least in the area of the serial read-in and read-out chains of the chip.

Abstract: A CCD storage module has storage positions which are arranged in cascade and which are produced by electrodes arranged in insulated fashion above a semiconductor substrate. In respect of each storage position, an item of information incoming as a n-digit binary number is stored in that a quantity of charge consisting of i unit charges is stored in respect of each storage position, where i corresponds to the value of the binary number of the information. A decoder circuit is provided for the input of the quantity of charge to the first storage position. The decoder circuit consists of n input circuits and each input circuit is assigned one bit position of the information composed of n bits and produces a charge corresponding to the digit value of that position.