Abstract: An automatic load detection system. A first reference signal that may be known apriori can be used for load detection. For example, the first reference signal may be used for invisible portion of a frame. The DAC receives the first reference signal and outputs a signal that is based on the first reference signal. The output of the DAC may have two known values depending on whether the load is coupled to the DAC, e.g., by having a different impedance. Thus, the output signal may be used for detecting whether the load is uncoupled from the DAC. If it is determined that the load is uncoupled from the DAC, the clocking signal to the DAC may be turned off. Thus, DAC no longer consumes power when the load is uncoupled, thereby saving power.

Abstract: Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detector (210); a sending circuit (220) that changes the value of a request signal (150) with each event; and a receiving circuit (230) that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter (410) that generates an incremental count (415) of event occurrences while a transfer is taking place; sending and receiving registers (420, 430, 530) for the incremental count; the request sending and receiving circuits (220, 230), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits (470, 480) for an acknowledgement signal.

Abstract: Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detector (210); a sending circuit (220) that changes the value of a request signal (150) with each event; and a receiving circuit (230) that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter (410) that generates an incremental count (415) of event occurrences while a transfer is taking place; sending and receiving registers (420, 430, 530) for the incremental count; the request sending and receiving circuits (220, 230), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits (470, 480) for an acknowledgement signal.

Abstract: An automatic load detection system. A first reference signal that may be known apriori can be used for load detection. For example, the first reference signal may be used for invisible portion of a frame. The DAC receives the first reference signal and outputs a signal that is based on the first reference signal. The output of the DAC may have two known values depending on whether the load is coupled to the DAC, e.g., by having a different impedance. Thus, the output signal may be used for detecting whether the load is uncoupled from the DAC. If it is determined that the load is uncoupled from the DAC, the clocking signal to the DAC may be turned off. Thus, DAC no longer consumes power when the load is uncoupled, thereby saving power.

Abstract: Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.

Abstract: Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.