Patents by Inventor Otto Torreiter
Otto Torreiter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10288684Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.Type: GrantFiled: November 8, 2017Date of Patent: May 14, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas Gentner, Daniel Rodko, Hagen Schmidt, Otto A. Torreiter
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Patent number: 10281527Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.Type: GrantFiled: June 16, 2017Date of Patent: May 7, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas Gentner, Daniel Rodko, Hagen Schmidt, Otto A. Torreiter
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Publication number: 20180364308Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Inventors: Thomas Gentner, Daniel Rodko, Hagen Schmidt, Otto A. Torreiter
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Publication number: 20180364309Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.Type: ApplicationFiled: November 8, 2017Publication date: December 20, 2018Inventors: Thomas Gentner, Daniel Rodko, Hagen Schmidt, Otto A. Torreiter
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Patent number: 10114069Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.Type: GrantFiled: December 10, 2015Date of Patent: October 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Eckhard Kunigkeit, Otto A. Torreiter, Quintino L. Trianni
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Patent number: 10114914Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.Type: GrantFiled: November 28, 2017Date of Patent: October 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
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Patent number: 10056346Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.Type: GrantFiled: February 20, 2017Date of Patent: August 21, 2018Assignee: International Business Machines CorporationInventors: Martin Eckert, Otto Torreiter, Quintino L. Trianni
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Patent number: 9977053Abstract: A wafer probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.Type: GrantFiled: June 8, 2016Date of Patent: May 22, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg G. Appinger, Eberhard Dengler, Roland Dieterle, Martin Eckert, Gabriele Kuczera, Siegfried Tomaschko, Otto Torreiter, Quintino Lorenzo Trianni
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Publication number: 20180107771Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.Type: ApplicationFiled: November 28, 2017Publication date: April 19, 2018Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
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Patent number: 9927463Abstract: A water probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.Type: GrantFiled: October 20, 2015Date of Patent: March 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg G. Appinger, Eberhard Dengler, Roland Dieterle, Martin Eckert, Gabriele Kuczera, Siegfried Tomaschko, Otto Torreiter, Quintino Lorenzo Trianni
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Patent number: 9904748Abstract: A layout effect characterization circuit includes a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.Type: GrantFiled: May 15, 2017Date of Patent: February 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
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Patent number: 9740813Abstract: An aspect includes forming a layout effect characterization circuit by incorporating a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain in an integrated circuit layout. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.Type: GrantFiled: October 13, 2016Date of Patent: August 22, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
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Patent number: 9709625Abstract: A method for determining power consumption of a power domain within an integrated circuit is presented. In a first step, a local power supply impedance profile (Z(f)) of this power domain is determined. Subsequently, a local time-resolved power supply voltage (U(t)) is measured while a well-defined periodic activity is executed in power domain. A set of time-domain measured voltage data (U(t)) is thus accumulated and transformed into the frequency domain to yield a voltage spectrum (U(f)). A current spectrum I(t) is calculated from this voltage profile (U(f)) by using the power supply impedance profile Z(f) of this power domain as I(t)=Ff?1{U(f)/Z(f)}. Finally, a time-resolved power consumption spectrum P(t) is determined from measured voltage spectrum U(t)) and calculated current spectrum (I(t)). This power consumption (P(t)) may be compared with a reference (Pref(t)) to verify whether power consumption within power domain matches expectations.Type: GrantFiled: June 28, 2011Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Martin Eckert, Roland Frech, Claudio Siviero, Jochen Supper, Otto A. Torreiter, Thomas-Michael Winkel
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Patent number: 9686895Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.Type: GrantFiled: September 4, 2013Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Martin Eckert, Otto Torreiter, Quintino L. Trianni
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Patent number: 9679665Abstract: A method including determining a test duration for testing each of a plurality of memory arrays individually coupled to a plurality of array built-in-self test (ABIST) engines, the test duration is equal to a time period required by each of the plurality of ABIST engines to test each of the plurality of memory arrays, determining a corresponding delay value for each of the plurality of ABIST engines, each of the corresponding delay values is based on the test duration for each of the plurality of memory arrays, and consecutively delaying the start of processing of each of the plurality of ABIST engines by providing each of the corresponding delay values to each of a plurality of programmable delay units individually coupled to each of the plurality of ABIST engines, the start of processing of each of the plurality of ABIST engines is delayed by a different corresponding delay value.Type: GrantFiled: October 29, 2014Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: Martin Eckert, Otto A. Torreiter, Christian Zoellin
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Publication number: 20170162534Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.Type: ApplicationFiled: February 20, 2017Publication date: June 8, 2017Inventors: Martin Eckert, Otto Torreiter, Quintino L. Trianni
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Publication number: 20170108534Abstract: A water probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.Type: ApplicationFiled: October 20, 2015Publication date: April 20, 2017Inventors: Joerg G. APPINGER, Eberhard DENGLER, Roland DIETERLE, Martin ECKERT, Gabriele KUCZERA, Siegfried TOMASCHKO, Otto TORREITER, Quintino Lorenzo TRIANNI
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Publication number: 20170108547Abstract: A wafer probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.Type: ApplicationFiled: June 8, 2016Publication date: April 20, 2017Inventors: Joerg G. APPINGER, Eberhard DENGLER, Roland DIETERLE, Martin ECKERT, Gabriele KUCZERA, Siegfried TOMASCHKO, Otto TORREITER, Quintino Lorenzo TRIANNI
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Patent number: 9627090Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.Type: GrantFiled: October 30, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Martin Eckert, Michael B. Kugel, Otto A. Torreiter, Tobias Werner
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Patent number: 9627017Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.Type: GrantFiled: September 24, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Martin Eckert, Michael B. Kugel, Otto A. Torreiter, Tobias Werner