Abstract: Aspects of the disclosure provide a method and system for power amplifier characterization and digital predistortion. The method includes receiving a test signal including K samples with a sampling rate fS, generating a synthetic test signal including the test signal and a sequence of (N?1) delayed versions of the test signal, generating an under-sampled signal including M samples by sampling, at a sampling rate fS/N, an output signal of a device-under-test (DUT) with the synthetic test signal as an input of the DUT, the M samples of the under-sampled signal including N segments each including K/N samples, and generating a reconstructed signal including the M samples of the under-sampled signal.

Abstract: Aspects of the disclosure provide a method and system for power amplifier characterization and digital predistortion. The method includes receiving a test signal including K samples with a sampling rate fS, generating a synthetic test signal including the test signal and a sequence of (N?1) delayed versions of the test signal, generating an under-sampled signal including M samples by sampling, at a sampling rate fS/N, an output signal of a device-under-test (DUT) with the synthetic test signal as an input of the DUT, the M samples of the under-sampled signal including N segments each including K/N samples, and generating a reconstructed signal including the M samples of the under-sampled signal.

Abstract: Aspects of the disclosure provide a method and system for power amplifier characterization and digital predistortion. The method includes receiving a test signal including K samples with a sampling rate fS, generating a synthetic test signal including the test signal and a sequence of (N?1) delayed versions of the test signal, generating an under-sampled signal including M samples by sampling, at a sampling rate fS/N, an output signal of a device-under-test (DUT) with the synthetic test signal as an input of the DUT, the M samples of the under-sampled signal including N segments each including K/N samples, and generating a reconstructed signal including the M samples of the under-sampled signal.

Abstract: Aspects of the disclosure provide a method and system for power amplifier characterization and digital predistortion. The method includes receiving a test signal including K samples with a sampling rate fS, generating a synthetic test signal including the test signal and a sequence of (N?1) delayed versions of the test signal, generating an undersampled signal including M samples by sampling, at a sampling rate fS/N, an output signal of a device-under-test (DUT) with the synthetic test signal as an input of the DUT, the M samples of the under-sampled signal including N segments each including K/N samples, and generating a reconstructed signal including the M samples of the under-sampled signal.

Abstract: Aspects of the disclosure provide a method and system for power amplifier characterization and digital predistortion. The method includes receiving a test signal including K samples with a sampling rate fS, generating a synthetic test signal including the test signal and a sequence of (N?1) delayed versions of the test signal, generating an under-sampled signal including M samples by sampling, at a sampling rate fS/N, an output signal of a device-under-test (DUT) with the synthetic test signal as an input of the DUT, the M samples of the under-sampled signal including N segments each including K/N samples, and generating a reconstructed signal including the M samples of the under-sampled signal.

Abstract: The behavioral model and predistorter for modeling and reducing nonlinear effects in power amplifiers addresses the model size estimation problem. The GMP model is replaced by the hybrid memory polynomial/envelope memory polynomial (HMEM) model within a twin nonlinear two-box structure to reduce the number of variables involved in the model size estimation problem, without compromising model accuracy and digital predistorter performance. A sequential approach is presented to efficiently estimate the model size. Experimental validation is carried out to evaluate the performance of the size estimation and the accuracy of the HMEM-based twin-nonlinear two-box model with respect to that of the GMP-based twin-nonlinear two-box model.

Abstract: The single-input single-output two-box polar behavioral model for envelope tracking power amplifiers estimates magnitude and phase of the output signal in separate paths. More specifically, the model is a two-box polar behavioral model using a complex magnitude and phase splitter that feeds a parallel combination of a generalized memory polynomial function and a memoryless polynomial function applied to the input signal's magnitude and phase, respectively. The present model is experimentally validated using a gallium nitride-based envelope tracking power amplifier driven by multi-carrier test signals.

Abstract: A system and method for linearizing a power amplifier using digital predistortion technique is provided including processing circuitry, the processing circuitry configured to apply a digital predistortion function based on a weighted static polynomial function, a weighted dynamic polynomial function and a threshold parameter which splits the nonlinear transfer characteristics of the device under test into a region where the static nonlinearity predominates and a region where the dynamic distortions predominate.

Abstract: Aspects of the disclosure provide a method and system for power amplifier characterization and digital predistortion. The method includes receiving a test signal including K samples with a sampling rate fS, generating a synthetic test signal including the test signal and a sequence of (N-1) delayed versions of the test signal, generating an under-sampled signal including M samples by sampling, at a sampling rate fS/N, an output signal of a device-under-test (DUT) with the synthetic test signal as an input of the DUT, the M samples of the under-sampled signal including N segments each including K/N samples, and generating a reconstructed signal including the M samples of the under-sampled signal.

Abstract: A system and method for linearizing a power amplifier using digital predistortion technique is provided including processing circuitry, the processing circuitry configured to apply a digital predistortion function based on a weighted static polynomial function, a weighted dynamic polynomial function and a threshold parameter which splits the nonlinear transfer characteristics of the device under test into a region where the static nonlinearity predominates and a region where the dynamic distortions predominate.

Abstract: The method for system level oriented load-pull-based envelope tracking power amplifiers includes steps of performing a multi-dimensional load-pull and selecting the reflection coefficients to be presented to the transistor while taking into account the system level architecture of the power amplifier. It is shown that adopting the proposed load reflection coefficient selection algorithm leads to an additional efficiency enhancement. This extra performance is achieved without additional circuitry or cost.

Abstract: A system and method for linearizing a power amplifier using digital predistortion technique is provided including processing circuitry, the processing circuitry configured to apply a digital predistortion function based on a weighted static polynomial function, a weighted dynamic polynomial function and a threshold parameter which splits the nonlinear transfer characteristics of the device under test into a region where the static nonlinearity predominates and a region where the dynamic distortions predominate.

Abstract: The behavioral model and predistorter for modeling and reducing nonlinear effects in power amplifiers addresses the model size estimation problem. The GMP model is replaced by the hybrid memory polynomial/envelope memory polynomial (HMEM) model within a twin nonlinear two-box structure to reduce the number of variables involved in the model size estimation problem, without compromising model accuracy and digital predistorter performance. A sequential approach is presented to efficiently estimate the model size. Experimental validation is carried out to evaluate the performance of the size estimation and the accuracy of the HMEM-based twin-nonlinear two-box model with respect to that of the GMP-based twin-nonlinear two-box model.

Abstract: The augmented twin nonlinear two-box modeling and predistortion method for power amplifiers and transmitters provides power amplifier distortion modeling and predistortion linearization. A memoryless nonlinearity is combined with a memory polynomial function that includes cross-terms. The method can utilize an augmented forward twin-nonlinear two-box model, an augmented reverse twin-nonlinear two-box model, or alternatively, an augmented parallel twin-nonlinear two-box model. The present two-box models are validated in modeling and predistortion applications. Measurement results demonstrate the superiority of the present two-box models with respect to conventional state of the art models. The present two-box models lead to better accuracy with reduced complexity.

Abstract: A system and method for linearizing a power amplifier using digital predistortion technique is provided including processing circuitry, the processing circuitry configured to apply a digital predistortion function based on a weighted static polynomial function, a weighted dynamic polynomial function and a threshold parameter which splits the nonlinear transfer characteristics of the device under test into a region where the static nonlinearity predominates and a region where the dynamic distortions predominate.

Abstract: The scalable digital predistortion system and method provides compensation for the nonlinear distortions of power amplifiers and transmitters. The scalable digital predistortion system and its associated update algorithms provide scalability in terms of signal bandwidth and average power, allowing for low complexity updates following changes in the signal's bandwidth and/or power level. The method applies both memory polynomial functions and memoryless predistortion functions for compensating for the nonlinear distortions.

Abstract: The digital predistortion system and method with extended correction bandwidth includes a predistortion system that uses a two-box architecture based on the cascade of a memory polynomial followed by a memoryless predistortion function. The memoryless predistorter is identified offline and used to perform a coarse linearization which cancels out most of the static nonlinearity of the device under test allowing for a reduced observation bandwidth for the synthesis of the memory polynomial predistortion sub-function.

Abstract: The memory polynomial based digital predistorter utilizes a cluster-based particle swarm optimization (PSO) technique and has an embedded model-size estimator. The PSO technique and model-size estimator efficiently find the dimensions and accurately estimate the coefficients of the memory polynomial based digital predistorter for improved linearity of a power amplifier.

Abstract: The system and method for joint compensation of power amplifier's distortion provides a linearization scheme for transmitter power amplifiers driven by orthogonal frequency division multiplexing signals. A pre-compensated over-driven amplifier is employed at the transmitter. The over-driven amplifier's distortions are considered as a sparse phenomenon and compressive sensing (CS) algorithms are employed at the receiver to estimate and compensate for these distortions. A bandwidth efficient data aided scheme which does not require reserving subcarriers specifically for CS measurements is utilized.

Abstract: The system and method for joint compensation of power amplifier's distortion provides a linearization scheme for transmitter power amplifiers driven by orthogonal frequency division multiplexing signals. A pre-compensated over-driven amplifier is employed at the transmitter. The over-driven amplifier's distortions are considered as a sparse phenomenon and compressive sensing (CS) algorithms are employed at the receiver to estimate and compensate for these distortions. A bandwidth efficient data aided scheme which does not require reserving subcarriers specifically for CS measurements is utilized.