Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding, reference source without any substantial affect upon its full scale output.

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding, reference source without any substantial affect upon its full scale output.

Abstract: Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.

Abstract: An output stage comprising a current mode line driver, a voltage mode line driver, and a center-tapped transformer for coupling data provided by the line drivers to a transmission line is provided herein. The output stage is configured to operate in a backwards compatible Ethernet communication device. For example, the Ethernet communication device is configured to support 10G Ethernet and legacy Ethernet modes of 10BASE-T, 100BASE-T, and 1000BASE-T. The current mode line driver can be utilized while operating in the 10G Ethernet mode to provide high linearity. The voltage mode line driver can be utilized while operating in legacy mode to conserve power. In order to accommodate the use of two different line drivers, a switch and/or a voltage regulator is used to couple/decouple a dc voltage to a center-tap of the transformer based on which of the two different line drivers is currently active.

Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.

Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.

Abstract: Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.

Abstract: An output stage comprising a current mode line driver, a voltage mode line driver, and a center-tapped transformer for coupling data provided by the line drivers to a transmission line is provided herein. The output stage is configured to operate in a backwards compatible Ethernet communication device. For example, the Ethernet communication device is configured to support 10G Ethernet and legacy Ethernet modes of 10BASE-T, 100BASE-T, and 1000BASE-T. The current mode line driver can be utilized while operating in the 10G Ethernet mode to provide high linearity. The voltage mode line driver can be utilized while operating in legacy mode to conserve power. In order to accommodate the use of two different line drivers, a switch and/or a voltage regulator is used to couple/decouple a dc voltage to a center-tap of the transformer based on which of the two different line drivers is currently active.

Abstract: A compact low-power class AB power amplifier design is provided. In an embodiment, the amplifier design eliminates an intermediate stage that couples an input stage and a biasing mesh of the amplifier. In another embodiment, the amplifier design reuses a tail current from the input stage to bias the biasing mesh. Accordingly, a much higher power efficiency can be achieved using the proposed amplifier design compared to conventional class AB amplifiers. Further, the proposed amplifier design is extremely compact and occupies a small silicon area.

Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

Abstract: A high efficiency class-AB amplifier is disclosed. The amplifier comprises a first input stage and a second input stage, both coupled to a class-AB biasing mesh and an output stage, wherein the outputs of the first and second input stages are directly coupled to the output transistors in the output stage. In one embodiment, a first gate of the first input stage and of the second input stage are coupled together to receive the same input and a second gate of the first input stage and of the second input stage are coupled together to receive the same input. In another embodiment, the first input stage and second input stage may further comprise cascode transistors for coupling the two input stages to the class-AB biasing mesh. In yet another embodiment, a 3V supply is used and 1V transistors are used to improve gain and 3V transistors are used to protect the 1V transistors.

Abstract: In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as ? ? ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an additional DAC cell is provided, which can be interchanged with each of the other DAC cells in order to switch each DAC cell successively from the multi-bit DAC into a calibration circuit to calibrate said DAC cell without interrupting the conversion. The calibration circuit includes means for measuring errors in the DAC cell under calibration and means for correcting said DAC cell.

Abstract: A compact low-power class AB power amplifier design is provided. In an embodiment, the amplifier design eliminates an intermediate stage that couples an input stage and a biasing mesh of the amplifier. In another embodiment, the amplifier design reuses a tail current from the input stage to bias the biasing mesh. Accordingly, a much higher power efficiency can be achieved using the proposed amplifier design compared to conventional class AB amplifiers. Further, the proposed amplifier design is extremely compact and occupies a small silicon area.

Abstract: Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.

Abstract: A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The digital-to-analog converter also receives a reference voltage reflecting variations of the supply voltage and adjusts its output signal accordingly to provide a deliberately variable analog voltage signal to the line driver.

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract: A high efficiency class-AB amplifier is disclosed. The amplifier comprises a first input stage and a second input stage, both coupled to a class-AB biasing mesh and an output stage, wherein the outputs of the first and second input stages are directly coupled to the output transistors in the output stage. In one embodiment, a first gate of the first input stage and of the second input stage are coupled together to receive the same input and a second gate of the first input stage and of the second input stage are coupled together to receive the same input. In another embodiment, the first input stage and second input stage may further comprise cascode transistors for coupling the two input stages to the class-AB biasing mesh. In yet another embodiment, a 3V supply is used and 1V transistors are used to improve gain and 3V transistors are used to protect the 1V transistors.

Abstract: A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The digital-to-analog converter also receives a reference voltage reflecting variations of the supply voltage and adjusts its output signal accordingly to provide a deliberately variable analog voltage signal to the line driver.