Abstract: An electronic circuit includes a differential output circuit that produces a differential output signal at a differential output. A primary winding of a balun has a first balun terminal coupled to a first differential output terminal, and a second balun terminal coupled to a second differential output terminal. A configurable harmonic reduction circuit includes first and second configurable shunt capacitance circuits coupled between the first differential output terminal or the second differential output terminal, respectively, and a ground reference node. A control circuit receives tuning data associated with a calibrated tuning state. The tuning data indicates a first and second calibrated capacitance values, which are unequal, for the first and second configurable shunt capacitance circuits, respectively.

Abstract: An electronic circuit includes a differential output circuit that produces a differential output signal at a differential output. A primary winding of a balun has a first balun terminal coupled to a first differential output terminal, and a second balun terminal coupled to a second differential output terminal. A configurable harmonic reduction circuit includes first and second configurable shunt capacitance circuits coupled between the first differential output terminal or the second differential output terminal, respectively, and a ground reference node. A control circuit receives tuning data associated with a calibrated tuning state. The tuning data indicates a first and second calibrated capacitance values, which are unequal, for the first and second configurable shunt capacitance circuits, respectively.

Abstract: A power amplification system includes a Power Amplifier (PA) for amplifying an input RF signal. An adaptive bias circuit is configured to adaptively set a bias of the PA. The adaptive biasing circuit includes a gain expansion circuit, a gain compression circuit and a biasing circuit. The gain expansion circuit derives a gain-expansion control signal from the input RF signal. For a first sub-range of the input RF signal, the gain-expansion control signal has a larger dynamic range than the input RF signal. The gain compression circuit derives a gain-compression control signal from the input RF signal. For a second sub-range of the input RF signal having higher power levels than the first sub-range, the gain-compression control signal has a smaller dynamic range than the input RF signal. The biasing circuit sets the bias of the PA responsively to the gain-expansion control signal and the gain-compression control signal.

Abstract: Radio-frequency front-end circuitry includes an output terminal, a receive amplifier controllably coupled to the output terminal, at least one transmit amplifier controllably inductively coupled to the output terminal, and at least one impedance element controllably coupled between ground and one of the at least one transmit amplifier to reduce degradation of output of the radio-frequency front-end circuitry when the at least one transmit amplifier is not in use. In differential signaling, there is an impedance element between ground and each pole of the differential signal. A second transmit amplifier may generate second transmit signals and harmonics of the second transmit signals, and the second transmit amplifier may be switchably connected to the output of a first transmit amplifier so that output of the second transmit amplifier is filtered by the one of the first transmit amplifier. The transmit amplifiers may include a WiFi power amplifier and a BLUETOOTH® power amplifier.

Abstract: A temperature sensor includes a current generator that detects a temperature and generates a temperature dependent current, the temperature dependent current having a current level corresponding to the detected temperature. A current-to-voltage converter converts the temperature dependent current into a temperature dependent voltage, the temperature dependent voltage having a voltage level corresponding to the detected temperature. A signal generator generates a pulse signal having a period determined from a voltage difference between the temperature dependent voltage and a reference voltage. A counter counts a number of cycles of a reference clock signal that occur during one cycle of the pulse signal to output a temperature code indicative of the temperature.

Abstract: The present disclosure includes systems and techniques relating to low power current-voltage mixed analog to digital converter (ADC) architecture. In some implementations, an ADC device includes a comparator array configured to receive an input analog voltage signal during a sample phase and a collection of reference voltages during a hold phase, a capacitor configured to receive the input analog voltage signal during the sample phase and to act as a feedback capacitor during the hold phase, an opamp coupled with the capacitor, and a transistor array configured to be powered by the opamp and activated by the comparator array to add or subtract currents to form a residue output voltage signal, which corresponds to the input analog voltage signal, used in analog to digital conversion of the input analog voltage signal.

Abstract: The present disclosure describes apparatuses and techniques for detection of an external oscillator. In some aspects, an integrated circuit includes an oscillator detector coupled to an external electrical connection. The oscillator detector may include a transistor having a gate coupled to the external electrical connection that is configured to detect a presence of an external oscillator.

Abstract: Methods and systems are described for providing an analog-to-digital converter that uses reduced power and supply voltage. In one embodiment, an analog-to-digital converter comprises a sample phase configured to sample an analog signal with at least three capacitors, wherein at least two of the three capacitors have unequal capacitance to cause the analog-to-digital converter to have a feedback factor that is greater than 1/3. The analog-to-digital converter also includes a feedback phase configured to produce a digital output signal based at least in part on the sampled analog signal, wherein the analog-to-digital converter is configured to operate with a supply voltage equal to about one half of an input signal voltage range of the analog signal.

Abstract: An IC includes first and second pads. The first pad is configured to receive an external clock. Alternatively, the first and second pads are configured to be coupled to a crystal oscillator and receive a reference clock. Alternatively, the second pad is configured to be grounded. The IC includes an internal oscillator for generating an internal clock, and an oscillator detector coupled to the second pad. The oscillator detector includes a transistor having a gate coupled to the second pad configured to pull a source-drain region to a first state if the second pad receives the reference clock or allow the source-drain region to be pulled to a second state if the second pad is grounded. The IC includes a buffer for transferring the first state to the internal oscillator for keeping the internal oscillator enabled and transferring the second state to the internal oscillator for disabling the internal oscillator.

Abstract: The present disclosure includes systems and techniques relating to low power current-voltage mixed ADC architecture. In some implementations, an apparatus includes sample and hold circuitry, at least one ADC module configured to generate a first digital output based on a first analog input provided to the sample and hold circuitry, and current generation circuitry configured to modulate an analog output of the sample and hold circuitry to generate a residue output corresponding to the first analog input absent at least a portion corresponding to the first digital output, and to provide the residue output as a second analog input to further circuitry to generate a second digital output.

Abstract: Methods and systems are described for providing an analog-to-digital converter that uses reduced power and supply voltage. The analog-to-digital converter includes a sample phase configured to sample an incoming analog signal having an input signal range and compare the incoming analog signal to a reference voltage. The analog-to-digital converter also includes a feedback phase wherein the feedback phase receives sampled signal data corresponding to the incoming analog signal from the sample phase and is configured to produce an output signal comprising an output signal range, wherein the output signal range is equal to one half of the input signal range, and wherein the analog-to-digital converter has a feedback factor that is substantially greater than ?.