Patents by Inventor Owai H. Low

Owai H. Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Insulated bonding wire tool for microelectronic packaging
    Patent number: 6991147
    Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: January 31, 2006
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Owai H. Low, Ramaswamy Ranganathan
  • Insulated bonding wire tool for microelectronic packaging
    Publication number: 20040182911
    Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
    Type: Application
    Filed: August 18, 2003
    Publication date: September 23, 2004
    Inventors: Chok J. Chia, Owai H. Low, Ramaswamy Ranganathan
  • Insulated bonding wire for microelectronic packaging
    Patent number: 6670214
    Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: December 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Owai H. Low, Ramaswamy Ranganathan
  • Thermally enhanced tape ball grid array package
    Patent number: 6002169
    Abstract: A semiconductor package (110) includes a tape substrate (135) having a top surface, a bottom surface, a plurality of conductive metal traces (115) formed on the top surface and a plurality of holes (130) arraigned in an array pattern formed through the tape substrate (135) exposing the conductive traces (115) from the bottom surface. A nonconductive metal plate or stiffener frame (155) attached to the bottom surface of the tape substrate (135) to support the tape substrate (135) during assembly. The stiffener frame (155) having through holes (160) corresponding to the holes (130) in the tape substrate (135) and being made from anodized aluminum, thus making it electrically nonconductive. An integrated circuit (IC) chip (120) is mounted on the top surface, opposite the stiffener frame (155).
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: December 14, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Owai H. Low