Patents by Inventor Owais E. Malik

Owais E. Malik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10838018
    Abstract: Examples described herein provide for testing of a test socket using multiple insertions to a contact resistance (CRES) test system. In an example, the test socket is placed in a first orientation on an interface board electrically connected to a test system. Using the test system and through the interface board, a first subset of probes of the test socket is tested while the test socket is in the first orientation on the interface board. The test socket is placed in a second orientation different from the first orientation on the interface board. Using the test system and through the interface board, a second subset of probes of the test socket is tested while the test socket is in the second orientation on the interface board. At least some probes of the second subset of probes are different from the first subset of probes.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 17, 2020
    Assignee: XILINX, INC.
    Inventors: David M. Mahoney, Joseph M. Juane, Owais E. Malik, Mohsen H. Mardi
  • Patent number: 10473713
    Abstract: An interposer block, a chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an interposer block for an integrated circuit chip package test system is provided. The interposer block includes a main body, a retainer plate, and a cover plate. A plurality of spring pins are each disposed in a respective one of a plurality of spring pin receiving holes formed in the main body. The retainer plate is coupled to the main body and captures the spring pins within the plurality of spring pin receiving holes. The cover plate is movably coupled to the main body. The cover plate has a plurality of spring pin clearance holes form therethrough that align with the plurality of spring pin receiving holes formed in the main body.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 12, 2019
    Assignee: XILINX, INC.
    Inventors: Alan Shu-Jen Chao, Owais E. Malik
  • Publication number: 20190128955
    Abstract: An interposer block, a chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an interposer block for an integrated circuit chip package test system is provided. The interposer block includes a main body, a retainer plate, and a cover plate. A plurality of spring pins are each disposed in a respective one of a plurality of spring pin receiving holes formed in the main body. The retainer plate is coupled to the main body and captures the spring pins within the plurality of spring pin receiving holes. The cover plate is movably coupled to the main body. The cover plate has a plurality of spring pin clearance holes form therethrough that align with the plurality of spring pin receiving holes formed in the main body.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Applicant: Xilinx, Inc.
    Inventors: Alan Shu-Jen Chao, Owais E. Malik