Abstract: A novel system for protecting one or more circuits during a dose rate event is presented. A clamping circuit is utilized that outputs a voltage signal that may be used to control prevent circuits from receiving input signals during a dose rate event. The clamping circuit comprises a photocurrent generating device that creates a current as a function of dose rate event strength. This current is used to control a grounding switch, which pulls the clamping circuit output to ground when a substantial current is created by the photocurrent generating device. The clamping circuit output may control a coupling switch that permits external input signal current flow when the clamping circuit output is above a threshold voltage level, and may prevent current flow when the output is grounded. The photocurrent generating device may be a PMOS device, while the coupling switch and clamping switch may be realized by NMOS devices.

Abstract: An MOS write transistor is connected to write coils of a magnetoresistive memory cell. The MOS write transistor controls passage of a write current into the write coils of the magnetoresistive memory cell. An array of MOS write transistors and an associated array of magnetoresistive memory cells are within a magnetoresistive memory array circuit.

Abstract: A magneto-resistive memory system is presented that includes a radiation-hardened and low power memory cell. The magneto-resistive memory cell includes a word line select transistor in the cell to help eliminate unselected cell disturbances. Furthermore, the magneto-resistive memory cell includes a full-turn write word line that writes true and complimentary bit values using less current than previous cell architectures. The improved memory cell may be used in a memory system with precision current drivers and auto-zero sense amplifiers in order to further lower power and improve overall system reliability.

Abstract: A device is connected in parallel with an MTJ structure of an MRAM bit to shunt photocurrent away from and/or limit voltage across the MTJ structure during a dose rate event. The device may include at least one transistor and/or at least one diode. One device may be used to protect an entire row and/or column of MRAM bits. As a result, the MRAM bits are protected during a dose rate event.

Abstract: A new read scheme is provided for an MRAM bit having a pinned layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis of the bit, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer.

Abstract: A high-voltage output buffer is implemented in a low-voltage semiconductor process. The buffer comprises a level translator circuit, the level translator operable to receive a signal varying between ground and a low voltage level, and to output a corresponding signal varying between a reference voltage level and a high voltage level. The reference voltage level is an intermediate voltage level between half of the low voltage level and the high voltage level. The buffer further comprises an output circuit operable to receive via an input the output of the level translator circuit, and to output a high voltage level when the input is a high voltage level or a zero voltage level when the input is at the reference voltage level.

Abstract: A circuit is protected from the application voltage from a high and a low voltage source that may power up at different times by supplying a circuit the applies an intermediate voltage whenever the high voltage has powered up when the low voltage has not until such time as the low voltage has powered up.

Abstract: A circuit for splitting a clock signal to produce two clock signals of differing phases that do not overlap one another. The circuit includes a NFET, a first PFET, a second NFET and a second PFET. The drain terminals of the first NFET and first PFET are coupled to one another and provide a clock signal FCLKN. The source terminal of the first NFET is coupled to ground, and the source terminal of the first PFET is coupled to the power supply voltage VDD. Similarly, the drain terminals of the second NFET and second PFET are coupled to one another and provide a clock signal FCLK. The source terminal of the second NFET is coupled to ground, and the source terminal of the second PFET is coupled to VDD. The gate terminal of either the first NFET or the first PFET is coupled to a master clock signal. The gate terminal of the other is coupled to the drains of the second NFET and second PFET. Similarly, the gate terminal of the corresponding second NFET or PFET is coupled to the complement of the master clock signal.