Patents by Inventor Oyekunle A. Olukotun

Oyekunle A. Olukotun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for simulation processor
    Patent number: 7043596
    Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: May 9, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas M. McWilliams, Jeffrey B. Rubin, Michael W. Parkin, Oyekunle A. Olukotun, Derek E. Pappas, Jeffrey M. Broughton, David R. Emberson, David S. Allison, Ashley N. Saulsbury, Earl T. Cohen, Nyles I. Nettleton, James B. Burr, Liang T. Chen
  • Method and apparatus for cycle-based computation
    Patent number: 7036114
    Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: April 25, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas M. McWilliams, Jeffrey B. Rubin, Derek E. Pappas, Oyekunle A. Olukotun, Jeffrey M. Broughton, David R. Emberson, William kwei-cheung Lam, Liang T. Chen, Ihao Chen, Earl T. Cohen, Michael W. Parkin
  • Method and apparatus for cycle-based computation
    Publication number: 20030040896
    Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.
    Type: Application
    Filed: March 29, 2002
    Publication date: February 27, 2003
    Inventors: Thomas M. McWilliams, Jeffrey B. Rubin, Derek E. Pappas, Oyekunle A. Olukotun, Jeffrey M. Broughton, David R. Emberson, William kwei-cheung Lam, Liang T. Chen, Ihao Chen, Earl T. Cohen, Michael W. Parkin
  • Method and apparatus for simulation processor
    Publication number: 20030040898
    Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.
    Type: Application
    Filed: March 29, 2002
    Publication date: February 27, 2003
    Inventors: Thomas M. McWilliams, Jeffrey B. Rubin, Michael W. Parkin, Oyekunle A. Olukotun, Derek E. Pappas, Jeffrey M. Broughton, David R. Emberson, David S. Allison, Ashley N. Saulsbury, Earl T. Cohen, Nyles I. Nettleton, James B. Burr, Liang T. Chen