Abstract: A method of establishing an asymmetric network between at least one node device and a gateway device is provided. The method may include transmitting a reduced data package from the node device, receiving the reduced data package in a data stream at the gateway device, validating bits of the data stream, and retrieving the reduced data package based on the validated bits.

Abstract: A method for pairing a first network device with a second network device is provided. The method may include receiving a first signal corresponding to a first pairing sequence received at the first network device, receiving a second signal corresponding to a second pairing sequence received at the second network device, comparing the first pairing sequence with the second pairing sequence, and pairing the first network device and the second network device when the second pairing sequence correlates to the first pairing sequence.

Abstract: A dynamic dithering method is provided for improving linearity in analog-to-digital converters.

Abstract: An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.

Abstract: Methods and apparatus are provided for calibrating stages in pipeline analog-to-digital converters (ADCs) having multiple channels.

Abstract: An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.

Abstract: A variable gain amplifier (VGA) disclosed herein includes: an input voltage connector; a number of voltage to current converter circuits generating signal currents; a gain adjustment connector adapted to a current steering mechanism; current mirrors connected to each of the voltage to current converters copying the signal currents; and a steering mechanism adapted to steer the copied currents to a load resistor or to another appropriate location based on the signal present at the gain adjustment connector.

Abstract: An analog-to-digital converter (ADC) apparatus comprising an input signal connector, an output signal port, two or more sub-ADCs, a digital signal processing (DSP) block, wherein the result from each sub-ADC is used by the DSP block to output data with increased performance and perform calibration of each sub-ADC independently while the other sub-ADCs and the DSP block operate and output data normally.

Abstract: A variable gain amplifier (VGA) disclosed herein includes an input current connector, an output current connector, a gain adjustment connector, scaled current mirrors copying the input current, means for steering the copied currents either to the current output or to another appropriate location based on the signal present at the gain adjustment connector.

Abstract: A circuit comprising an input, two or more sampling capacitors, means for connecting each sampling capacitor to said input, means for discharging the sampling capacitors to a given voltage in a reset phase, means to use the voltage across the sampling capacitor for further processing in a hold phase, operating the two sampling capacitors in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in hold phase.

Abstract: An embodiment of an LNA includes a voltage input, a voltage output, an input transistor connected as a source follower with a current source at the drain and source nodes of the input transistor, an input resistor connected between the source follower source node and signal ground, a gain boosting transistor with the gate connected to the input transistor drain node, wherein the source node is connected to ground and the drain node is connected through a load resistor to the input transistor source node. Such an LNA provides substantial improvement in power efficiency by adapting an output stage of the LNA to reuse the supply current of the input transistors to the LNA through a load resistor.

Abstract: An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.

Abstract: An embodiment of an LNA includes a voltage input, a voltage output, an input transistor connected as a source follower with a current source at the drain and source nodes of the input transistor, an input resistor connected between the source follower source node and signal ground, a gain boosting transistor with the gate connected to the input transistor drain node, wherein the source node is connected to ground and the drain node is connected through a load resistor to the input transistor source node. Such an LNA provides substantial improvement in power efficiency by adapting an output stage of the LNA to reuse the supply current of the input transistors to the LNA through a load resistor.

Abstract: A variable gain amplifier (VGA) disclosed herein includes: an input voltage connector; a number of voltage to current converter circuits generating signal currents; a gain adjustment connector adapted to a current steering mechanism; current mirrors connected to each of the voltage to current converters copying the signal currents; and a steering mechanism adapted to steer the copied currents to a load resistor or to another appropriate location based on the signal present at the gain adjustment connector.

Abstract: A variable gain amplifier (VGA) disclosed herein includes an input current connector, an output current connector, a gain adjustment connector, scaled current mirrors copying the input current, means for steering the copied currents either to the current output or to another appropriate location based on the signal present at the gain adjustment connector.

Abstract: A switched Capacitor Track and Hold Amplifier having at least one signal input, at least one clock input and an output, comprising a sampling capacitor, a buffer amplifier connected between the input signal and the first plate of the sampling capacitor having high output impedance in the odd clock phase, a switch connected between the second plate of the sampling capacitor and a signal ground being closed in the even clock phase, means for copying the sampled input voltage to the output in the hold phase and means for controlling the output impedance of the input buffer amplifiers.