Patents by Inventor Oz Dov Hershkovitz

Oz Dov Hershkovitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11487276
    Abstract: A method of salvaging an output is provided. The method includes defining a condition for terminating a run of a tool, checking whether the condition is likely to be met during a running of the tool, terminating the running in an event the condition is likely to be met, checking a validity of an incomplete output of the tool generated during the running and finalizing the incomplete output in an event the incomplete output is valid.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Oz Dov Hershkovitz
  • Patent number: 11361136
    Abstract: An approach to create a multiple use test case when one or more computer processors receive a first test case from a test generator. The approach includes the computer processors evaluating each instruction in the first test case to determine that an instruction meets a set of conditions for creating a multiple use test case. The method includes one or more computer processors generating a set of rules for each instruction meeting the one or more conditions to create the multiple use test case. Furthermore, the method includes one or more computer processors creating the multiple use test case by adding the set of rules to each instruction meeting the one or more conditions to create the multiple use test case.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventor: Oz Dov Hershkovitz
  • Publication number: 20220019721
    Abstract: An approach to create a multiple use test case when one or more computer processors receive a first test case from a test generator. The approach includes the computer processors evaluating each instruction in the first test case to determine that an instruction meets a set of conditions for creating a multiple use test case. The method includes one or more computer processors generating a set of rules for each instruction meeting the one or more conditions to create the multiple use test case. Furthermore, the method includes one or more computer processors creating the multiple use test case by adding the set of rules to each instruction meeting the one or more conditions to create the multiple use test case.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Inventor: Oz Dov Hershkovitz
  • Patent number: 11188304
    Abstract: Validating microprocessor instruction execution by receiving a floating-point exception selection, receiving a validation method selection, generating validation data according to the floating-point exception selection and the validation method selection by randomly generating a first tensor element value and randomly generating a second tensor element value according to the first tensor element value and the floating-point exception selection, and executing a floating-point computation according to the validation data.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gal Ashour, Oz Dov Hershkovitz, Michal Rimon, Karen Holtz, Silvia Melitta Mueller, Avishai Moshe Fedida
  • Patent number: 11169909
    Abstract: A method for flexible test program generation is described that alters previously used resources. The method includes scanning, by a test generator, a set of instructions that have been executed by a system under test (SUT) using a reference model of the SUT. The method further includes identifying, by the test generator, a resource for using in a test program by determining an allocation of a first value to the resource by a subset of instructions from the set of instructions, wherein the first value of the resource is not used after the allocation. The method further includes modifying the subset of instructions to allocate a second value to the resource, and adding to the set of instructions, at least one instruction that uses the second value to perform a predetermined operation. The SUT is tested based on a result of the predetermined operation that uses the second value.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oz Dov Hershkovitz, Ofer Peled
  • Publication number: 20210303449
    Abstract: A method for flexible test program generation is described that alters previously used resources. The method includes scanning, by a test generator, a set of instructions that have been executed by a system under test (SUT) using a reference model of the SUT. The method further includes identifying, by the test generator, a resource for using in a test program by determining an allocation of a first value to the resource by a subset of instructions from the set of instructions, wherein the first value of the resource is not used after the allocation. The method further includes modifying the subset of instructions to allocate a second value to the resource, and adding to the set of instructions, at least one instruction that uses the second value to perform a predetermined operation. The SUT is tested based on a result of the predetermined operation that uses the second value.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: OZ DOV HERSHKOVITZ, OFER PELED
  • Publication number: 20210278831
    Abstract: A method of salvaging an output is provided. The method includes defining a condition for terminating a run of a tool, checking whether the condition is likely to be met during a running of the tool, terminating the running in an event the condition is likely to be met, checking a validity of an incomplete output of the tool generated during the running and finalizing the incomplete output in an event the incomplete output is valid.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Inventor: Oz Dov Hershkovitz
  • Patent number: 9117023
    Abstract: A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a computerized system that comprises a template segment comprising instructions and directives or related control constructs; a test generator for generating a test associated with the template segment, comprising: a simulator for determining a state of the system associated with an execution of the test; a selector for selecting a template instruction or segment from the test template based on the state of the system; and a generator configured to generate a multiplicity of instructions based on system's state and on the selected template segment, wherein the test generator further comprises a verifier configured to verify that a previously generated instruction is in line with the current state of the system and with the selected template instruction or segment.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventors: Oz Dov Hershkovitz, Yoav Avraham Katz
  • Patent number: 8707101
    Abstract: Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eli Almog, Oz Dov Hershkovitz, Christopher Krygowski
  • Publication number: 20120117427
    Abstract: Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 10, 2012
    Inventors: Eli Almog, Oz Dov Hershkovitz, Christopher Krygowski