Patents by Inventor P. A. Patton
P. A. Patton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11986053Abstract: Foot support systems, e.g., for articles of footwear, include systems for changing the hardness or firmness of the foot support portion (e.g., of a sole structure) and/or systems for moving (e.g., selectively moving) fluid between various portions of the foot support system.Type: GrantFiled: December 15, 2021Date of Patent: May 21, 2024Assignee: NIKE, Inc.Inventors: Olivier Henrichot, Timothy P. Hopkins, Elizabeth Langvin, Austin Orand, Levi J. Patton
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Publication number: 20240139608Abstract: The present disclosure generally relates to user interfaces for managing, modifying, and/or outputting workout content.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Craig D. BOLTON, Julie A. ARNEY, Edward CHAO, Lynne DEVINE, Victoria E. HINN, Daniel S. KEEN, Julia K. NICHOLS, James P. OCHS, Jennifer D. PATTON
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Patent number: 11969053Abstract: Foot support systems, e.g., for articles of footwear, include systems for changing the hardness or firmness of the foot support portion (e.g., of a sole structure) and/or systems for moving (e.g., selectively moving) fluid between various portions of the foot support system.Type: GrantFiled: November 23, 2021Date of Patent: April 30, 2024Assignee: NIKE, Inc.Inventors: Olivier Henrichot, Timothy P. Hopkins, Elizabeth Langvin, Austin Orand, Levi J. Patton
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Patent number: 8102009Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.Type: GrantFiled: October 3, 2006Date of Patent: January 24, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Simon Siu-Sing Chan, Paul R. Besser, Jeffrey P. Patton
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Patent number: 7843015Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.Type: GrantFiled: September 15, 2005Date of Patent: November 30, 2010Assignee: GLOBALFOUNDRIES Inc.Inventors: Robert J. Chiu, Paul R. Besser, Simon Siu-Sing Chan, Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Errol Todd Ryan
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Patent number: 7307322Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.Type: GrantFiled: October 17, 2005Date of Patent: December 11, 2007Assignee: Adavnced Micro Devices, Inc.Inventors: Robert J. Chiu, Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo
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Patent number: 7151020Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.Type: GrantFiled: May 4, 2004Date of Patent: December 19, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Robert J. Chiu, Errol Todd Ryan, Darin A. Chan, Paul R. Besser, Paul L. King, Minh Van Ngo
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Patent number: 7132352Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.Type: GrantFiled: August 6, 2004Date of Patent: November 7, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Simon Siu-Sing Chan, Paul R. Besser, Jeffrey P. Patton
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Patent number: 7064067Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.Type: GrantFiled: February 2, 2004Date of Patent: June 20, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Paul L. King, Simon Siu-Sing Chan, Jeffrey P. Patton, Minh Van Ngo
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Patent number: 7049666Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.Type: GrantFiled: June 1, 2004Date of Patent: May 23, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Robert J. Chiu, Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo
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Patent number: 7023059Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.Type: GrantFiled: March 1, 2004Date of Patent: April 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Darin A. Chan, Simon Siu-Sing Chan, Jeffrey P. Patton, Jacques J. Bertrand
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Patent number: 7005376Abstract: A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.Type: GrantFiled: July 7, 2003Date of Patent: February 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Robert J. Chiu, Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo
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Patent number: 6969678Abstract: A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.Type: GrantFiled: November 3, 2003Date of Patent: November 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Robert J. Chiu, Paul R. Besser, Simon Siu-Sing Chan, Jeffrey P. Patton, Austin C. Frenkel, Thorsten Kammler, Errol Todd Ryan
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Patent number: 6528088Abstract: Film-forming compositions are disclosed that can comprise, on a dry solids basis, 25 to 75 percent by weight of certain starch derivatives and 25 to 75% primary external plasticizer. The starch derivatives can be chemically modified starches that range in molecular weight from 100,000 to 2,000,000. The high levels of plasticizer in the films give excellent film flexibility and integrity.Type: GrantFiled: June 1, 2000Date of Patent: March 4, 2003Assignee: A. E. Staley Manufacturing Co.Inventors: G. M. Gilleland, J. L. Turner, P. A. Patton, M. D. Harrison
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Publication number: 20020142031Abstract: Film-forming compositions are disclosed that can comprise, on a dry solids basis, 25 to 75 percent by weight of certain starch derivatives and 25 to 75% primary external plasticizer. The starch derivatives can be chemically modified starches that range in molecular weight from 100,000 to 2,000,000. The high levels of plasticizer in the films give excellent film flexibility and integrity. The films are also resistant to penetration by water, oil and/or grease.Type: ApplicationFiled: February 26, 2001Publication date: October 3, 2002Inventors: G. M. Gilleland, J. L. Turner, P. A. Patton, M. D. Harrison
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Patent number: 4760746Abstract: A torque to yield indicator and method. An indicator and dial members are coaxially mounted relative to the shank of a torque wrench. One corotates with the shank; the other is freewheeling. After the specified torque load is applied to a fastener, the freely rotatable member is held against movement. When the torque wrench is further rotated, the dial and scale on the members show the amount of relative angular movement which is stopped when the preselected amount of rotation has occurred.Type: GrantFiled: February 17, 1987Date of Patent: August 2, 1988Assignee: Fel-Pro IncorporatedInventors: Gregory M. Kruse, Harold P. Patton