Patents by Inventor P. Divakaran

P. Divakaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080029403
    Abstract: A method of taking inoperative pot online using fuse in an aluminium manufacturing plant operating on electrolysis process is disclosed. The manufacturing plant comprises of plurality of electrolysis cells or pots connected in series. Some of the pots are kept off line during start up of the plant by shorting the risers of the non running pots to the cathode bus bar (31) by shorted joints (11). The method comprises, connecting fuse assemblies in parallel with the shorted joints; inserting insulating insert plates between the risers and the short circuit bus bars and securing the insulating insert plates to isolate the short circuit bus bars from the risers (14) such that the total rated current passes through the fuse assemblies. The fuse elements in the fuse assemblies melt within about 8 to 10 minutes, completely isolating the short circuit bus bars from the risers such that the risers now feed the current to the anode assemblies of the non running pot.
    Type: Application
    Filed: July 11, 2007
    Publication date: February 7, 2008
    Applicant: Bharat Aluminium Company Limited
    Inventors: J. Ramaswamy, P. Divakaran
  • Patent number: 7250348
    Abstract: A method and apparatus for packaging semiconductor devices using patterned laminate films to reduce stress buffering. The method includes fabricating a semiconductor die having thin film resistors and bond pads formed on an active surface. A film layer is formed onto the active surface of the die, covering the thin film resistors and bond pads. The film layer is then patterned to create recesses in the film layer in the vicinity of the bond pads on the active surface of the die. The die then undergoes wire bonding and is next encapsulated in a molding compound. The film layer between the film resister and the molding compound reduces stress buffering created by the molding compound.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: July 31, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Zabarulla Hanifah, Pradeep A/L P. Divakaran, Low Chian Inn, Lim Leong Heng