Abstract: A mechanism for executing computer instructions in parallel includes a compiler for generating and grouping instructions into a plurality of sets of instructions to be executed in parallel, each set having a unique identification. A computer system having a real state and a speculative state executes the sets in parallel, the computer system executing a particular set of instructions in the speculative state if the instructions of the particular set have dependencies which can not be resolved until the instructions are actually executed. The computer system generates speculative data while executing instructions in the speculative state. Logic circuits are provided to detect any exception conditions which occur while executing the particular set in the speculative state. If the particular set is subject to an exception condition, the instructions of the set are re-executed to resolve the exception condition, and to incorporate the speculative data in the real state of the computer system.

Abstract: A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.

Abstract: An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.